Self-aligned metal oxide TFT with reduced number of masks and with reduced power consumption
A method of fabricating MO TFTs includes positioning opaque gate metal on a transparent substrate to define a gate area. Depositing gate dielectric material overlying the gate metal and a surrounding area, and depositing metal oxide semiconductor material thereon. Depositing etch stop material on the semiconductor material. Positioning photoresist defining an isolation area in the semiconductor material, the etch stop material and the photoresist being selectively removable. Exposing the photoresist from the rear surface of the substrate and removing exposed portions to leave the etch stop material uncovered except for a portion overlying and aligned with the gate metal. Etching uncovered portions of the semiconductor material to isolate the TFT. Using the photoresist, selectively etching the etch stop layer to leave a portion overlying and aligned with the gate metal and defining a channel area in the semiconductor material. Depositing and patterning conductive material to form source and drain areas.
1. An active matrix backpanel including an array of metal oxide TFTs with reduced inter-electrode capacitance, each TFT of the array of TFTs comprising:
a transparent substrate having a front surface and a rear surface;
an opaque gate metal positioned on the front surface of the substrate and defining a gate area for the TFT and gate selection bus-lines of the active matrix;
a layer of transparent gate dielectric material positioned on the front surface of the substrate overlying the gate metal and a surrounding area;
a layer of transparent metal oxide semiconductor material positioned on the surface of the layer of transparent gate dielectric;
a layer of etch stop material positioned on the layer of metal oxide semiconductor material overlying and aligned with the gate metal, the layer of the etch stop material defining a channel area in the layer of metal oxide semiconductor material; and
conductive material patterned to form data lines of the active matrix crossing over the gate/selection lines and source/drain electrodes on opposed sides of the channel area of each TFT, wherein the source/drain contacts are aligned on a portion of the etch stop layer overlying and aligned with the gate metal and on the layer of metal oxide semiconductor material.
2. The active matrix backpanel as claimed in claim 1 further including a transparent pixel electrode patterned within a transparent zone defined by the data lines and gate/selection lines in each TFT of the array of TFTs.
3. The active matrix backpanel as claimed in claim 1 wherein the transparent substrate is a glass or a plastic sheet, or combination thereof in stack form.
4. The active matrix backpanel as claimed in claim 1 wherein the transparent gate dielectric layer comprises SiN, SiO 2 , SiON, Al 2 O 3 , ZrO 2 , Ta 2 O 5 , T i O 2 in single layer or in multiple stack form.
5. The active matrix backpanel as claimed in claim 1 wherein the gate dielectric layer is a self-aligned surface chemical reaction material overlying top and side walls of the gate metal layer.
6. The active matrix backpanel as claimed in claim 1 wherein the gate dielectric layer includes a thermal oxidation material, plasma oxidation material, anodization material and their combinations.
7. The active matrix backpanel as claimed in claim 1 wherein the layer of transparent metal oxide semiconductor material includes ZnO, InO, SnO, GaO, AlZnO, GaInO, GaZnO, ZnInO, InAlZnO, InGaSnO, InAlSnO, InGaZnO, ZnSnO, GaSnO, InGaCuO, InCuO, AlSnO, and AlCuO in single layer with uniform composition or in blend or multiple stack form.
8. The active matrix backpanel as claimed in claim 1 wherein the layer of etch stop material comprises a transparent inorganic dielectric layer, or a transparent organic dielectric layer, or combinations thereof in multiple stack or in blend form.
9. The active matrix backpanel as claimed in claim 8 wherein the transparent etch-stop layer comprises PMGI, polystyrene (PS), Poly(methyl methacrylate)(PMMA), polyimide (PI), polyethylene (PE), spin on glass, poly-acrylics, MgF 2 , Ta 2 O 5 , TiO 2 , ZrO 2 , V 2 O 5 , W 2 O 3 , SiO 2 , SiN, SiON, Al 2 O 3 , AlN in single or multiple-stack form.
10. The active matrix backpanel as claimed in claim 1 wherein the layer of etch stop material includes a layer with a thickness greater than the thickness of the layer of transparent gate dielectric material.
11. An active matrix backpanel as claimed in claim 1 wherein the layer of etch stop material has a thickness greater than twice as thick as the thickness of the gate dielectric material.
12. An active matrix backpanel as claimed in claim 1 wherein the layer of etch stop material has a thickness of at least 500 nm.
13. An active matrix backpanel as claimed in claim 1 wherein the layer of etch stop material includes a material with a lower dielectric constant than a dielectric constant of the transparent gate dielectric material.
14. The active matrix backpanel of claim 1 incorporated in a thin film electronic device.
15. The active matrix backpanel as claimed in claim 14 wherein thin film electronic device is an active matrix display, an active matrix image array, a chemical sensor array or a bio-sensor array.