Semiconductor devices FinFET devices with optimized strained-sourece-drain recess profiles and methods of forming the same

1. A semiconductor device, comprising:

a substrate;

a gate stack over the substrate; and

a strained layer in a recess of the substrate and aside the gate stack,

wherein a ratio of a depth at the greatest width of the recess to a width of the gate stack ranges from about 0.5 to 0.7,

wherein the semiconductor device further comprises a spacer on a sidewall of the gate stack, a top edge of the recess is covered by and spaced apart from an outer edge of the spacer, a sidewall of the recess connecting the top edge and a bottom edge of the recess is a curved surface without a sharp turning point, and an included angle between an upper portion of the sidewall of the recess and a surface of the substrate is from about 50 degrees to 90 degrees, and

wherein the substrate is a substrate with at least one fin extending in a first direction, and the gate stack extends in a second direction different from the first direction and is across the at least one fin.

2. The semiconductor device of claim 1 , wherein a top width of the recess is smaller than a middle width of the recess.

3. A FinFET device, comprising:

a substrate having at least one fin;

two gate stacks across the at least one fin; and

a strained layer in a recess of the substrate and between the gate stacks,

wherein a ratio of a width of the gate stacks to the greatest width of the recess ranges from about 0.4 to 0.6,

wherein the FinFET device further comprises spacers on sidewalls of the gate stacks, a top edge of the recess is covered by and spaced apart from outer edges of the spacers, a sidewall of the recess connecting the top edge and a bottom edge of the recess is a curved surface without a sharp turning point, and an included angle between an upper portion of the sidewall of the recess and a surface of the substrate is from about 50 degrees to 90 degrees.

4. The FinFET device of claim 3 , wherein a ratio of a depth at the greatest width of the recess to the width of the gate stacks ranges from about 0.5 to 0.7.

5. The FinFET device of claim 3 , wherein a ratio of a depth at the greatest width of the recess to a total depth of the recess ranges from about ¼ to ⅓.

6. The FinFET device of claim 3 , wherein a middle width of the recess is greater than each of a top width and a bottom width of the recess.

7. The FinFET device of claim 3 , wherein the greatest width of the recess is no more than a distance between the gate stacks.

8. A method of forming a FinFET device, comprising:

providing a substrate having a gate stack formed thereon;

performing a first etching step to form a recess in the substrate aside the gate stack, wherein a ratio of a width of the gate stack to a depth of the recess ranges from about 0.4 to 0.7;

performing a second etching step to deepen and widen the recess, wherein a top edge of the recess after the second etching step is covered by and spaced apart from an outer edge of a spacer on a sidewall of the gate stack, a sidewall of the recess connecting the top edge and a bottom edge of the recess is a curved surface without a sharp turning point, and an included angle between an upper portion of the sidewall of the recess and a surface of the substrate is from about 50 degrees to 90 degrees; and

forming a strained layer in the recess.

9. The method of claim 8 , wherein the first etching step comprises an anisotropic etching process.

10. The method of claim 8 , wherein the second etching step comprises an isotropic etching process.

11. The method of claim 8 , wherein the recess has a wide-middle profile after the second etching step.