Encoder having phase adjuster for offsetting phases of multi-phase input signal
A resistor string outputs sixteen signals with a phase difference of 22.5° by dividing voltage between two adjacent phases of a four-phase input signal with a phase difference of 2π/M (where M is an integer equal to or greater than 2), and by generating four signals with a delayed phase for each phase of the four-phase input signal. A switch portion selects four signals with a phase difference of 90° from the sixteen signals. Amplifiers output each of the four signals, which are attenuated by dividing the voltage with the resistor string, as a four-phase output signal by amplifying each of the four signals such that an amplitude of the four signals matches the amplitude of the four-phase input signal.
1. A phase adjuster, comprising:
a resistor string configured to output an MN number of signals with a phase difference of 2π/MN by dividing voltage between two adjacent phases of an M-phase input signal with a phase difference of 2π/M, where MN is the product of M and N, and M is an integer of at least 2, the resistor string further configured to generate an N number of signals, where N is an integer of at least 2 with a phase delay for each of the phases of the M-phase input signal;
a switch configured to select an L number of signals with a phase difference of 2π/L, where L is an integer of at least 2, from the MN signals; and
an L number of amplifiers configured to output an L-phase output signal, where L is the integer of at least 2, by amplifying each of the L number of signals attenuated by dividing the voltage with the resistor string such that an amplitude of the L number of signals matches the amplitude of the M-phase input signal.
2. A phase adjuster, comprising:
a resistor string configured to output an MN number of signals with a phase difference of 2π/MN by dividing voltage between two adjacent phases of an M-phase input signal with a phase difference of 2π/M, where MN is the product of M and N, and M is an integer of at least 2, the resistor string further configured to generate an N number of signals, where N is an integer of at least 2 with a phase delay for each of the phases of the M-phase input signal;
a switch configured to select an L number of signals with a phase difference of 2π/L, where L is an integer of at least 2, from the MN signals; and
an L number of amplifiers configured to output an L-phase output signal, where L is the integer of at least 2, by amplifying each of the L number of signals attenuated by dividing the voltage with the resistor string such that an amplitude of the L number of signals matches the amplitude of the M-phase input signal,
wherein a first phase, which is one of the two adjacent phases of the M-phase input signal, is inputtable to a first end of an N number of serially connected resistors, and
a second phase, which is another phase of the two adjacent phases of the M-phase input signal, is inputtable to a second end of the N number of serially connected resistors.
3. The phase adjuster according to claim 2 ,
wherein when a combined resistance of the N number of serially connected resistors is defined as R TOTAL , a combined resistance R E of a k number of resistors, which is counted kth from the first phase side, where k is an integer fulfilling a relationship 1≤k≤N, among the N number of serially connected resistors, is expressed by:
R
E
=
R
TOTAL
·
sin
2
π
M
sin
2
π
k
MN
+
sin
(
2
π
M
-
2
π
k
MN
)
·
sin
2
π
k
MN
sin
2
π
M
=
R
TOTAL
·
sin
2
π
k
MN
sin
2
π
k
MN
+
sin
(
2
π
M
-
2
π
k
MN
)
,
(
1
)
and
wherein Rk is a resistance value of the kth resistor, as counted from the first phase side among the N number of serially connected resistors, and is expressed by:
Rk
=
R
E
-
∑
i
=
1
k
-
1
R
i
.
(
2
)
4. The phase adjuster according to claim 3 ,
wherein each of the L number of amplifiers is configured to amplify a signal being output from between the kth resistor and a k+1th resistor, as counted from the first phase side, by 1/β k , and β k is expressed below as:
β
k
=
sin
2
π
M
sin
2
π
k
MN
+
sin
(
2
π
M
-
2
π
k
MN
)
.
(
3
)
5. The phase adjuster according to claim 2 ,
wherein the MN number of resistors in the resistor string are serially connected in a ring shape, and
the switch is a rotary switch including a terminal which is connectable to a node separated by an MN/L number of nodes among the MN number of nodes between the MN number of resistors.
6. The phase adjuster according to claim 3 ,
wherein the MN number of resistors in the resistor string are serially connected in a ring shape, and
the switch is a rotary switch including a terminal which is connectable to a node separated by an MN/L number of nodes among the MN number of nodes between the MN number of resistors.
7. The phase adjuster according to claim 4 ,
wherein the MN number of resistors in the resistor string are serially connected in a ring shape, and
the switch is a rotary switch including a terminal which is connectable to a node separated by an MN/L number of nodes among the MN number of nodes between the MN number of resistors.
8. An encoder, comprising:
a phase adjuster, including
a resistor string configured to output an MN number of signals with a phase difference of 2π/MN by dividing voltage between two adjacent phases of an M-phase input signal with a phase difference of 2π/M, where MN is the product of M and N, and M is an integer of at least 2, the resistor string further configured to generate an N number of signals, where N is an integer of at least 2 with a phase delay for each of the phases of the M-phase input signal;
a switch configured to select an L number of signals with a phase difference of 2π/L, where L is an integer of at least 2, from the MN signals; and
an L number of amplifiers configured to output an L-phase output signal, where L is the integer of at least 2, by amplifying each of the L number of signals attenuated by dividing the voltage with the resistor string such that an amplitude of the L number of signals matches the amplitude of the M-phase input signal;
a detector configured to read and output an origin point signal and the M-phase input signal, which is a main signal; and
an origin point signal synchronizer configured to determine a position of the origin point by synchronizing the origin point signal and the L-phase output signal.
9. An encoder, comprising:
the phase adjuster according to claim 2 ;
a detector configured to read and output an origin point signal and the M-phase input signal, which is a main signal; and
an origin point signal synchronizer configured to determine a position of the origin point by synchronizing the origin point signal and the L-phase output signal.
10. An encoder, comprising:
the phase adjuster according to claim 3 ;
a detector configured to read and output an origin point signal and the M-phase input signal, which is a main signal; and
an origin point signal synchronizer configured to determine a position of the origin point by synchronizing the origin point signal and the L-phase output signal.
11. An encoder, comprising:
the phase adjuster according to claim 4 ;
a detector configured to read and output an origin point signal and the M-phase input signal, which is a main signal; and
an origin point signal synchronizer configured to determine a position of the origin point by synchronizing the origin point signal and the L-phase output signal.
12. An encoder, comprising:
the phase adjuster according to claim 5 ;
a detector configured to read and output an origin point signal and the M-phase input signal, which is a main signal; and
an origin point signal synchronizer configured to determine a position of the origin point by synchronizing the origin point signal and the L-phase output signal.
13. An encoder, comprising:
the phase adjuster according to claim 6 ;
a detector configured to read and output an origin point signal and the M-phase input signal, which is a main signal; and
an origin point signal synchronizer configured to determine a position of the origin point by synchronizing the origin point signal and the L-phase output signal.
14. An encoder, comprising:
the phase adjuster according to claim 7 ;
a detector configured to read and output an origin point signal and the M-phase input signal, which is a main signal; and
an origin point signal synchronizer configured to determine a position of the origin point by synchronizing the origin point signal and the L-phase output signal.