Mask patterns generated in memory from seed vectors
The present disclosure includes apparatuses and methods related to mask patterns generated in memory from seed vectors. An example method includes performing operations on a plurality of data units of a seed vector and generating, by performance of the operations, a vector element in a mask pattern.
1. A method, comprising:
performing a set of operations, including a plurality of different operations, on a plurality of data units of a single seed vector having a predetermined data unit at each bit position, wherein the single seed vector includes a continuous series of the data units on which the set including the plurality of different operations is performed to generate a plurality of mask patterns having different bit interval lengths of vector elements; and
generating, by performance of the set including the plurality of different operations, a vector element including a plurality of data units in a mask pattern.
2. The method of claim 1 , wherein the method further comprises storing the plurality of data units of the single seed vector as a continuous series of data units.
3. The method of claim 1 , wherein the method further comprises storing the plurality of data units of the single seed vector in a corresponding plurality of memory cells.
4. The method of claim 1 , wherein the method further comprises storing the plurality of data units of the single seed vector in a corresponding plurality of at least one of a sense amplifier and a compute component in sensing circuitry.
5. The method of claim 1 , wherein the method further comprises generating a repeating mask pattern that comprises a plurality of adjacent generated vector elements therein.
6. The method of claim 1 , wherein the method further comprises:
identifying a high bit indicator associated with at least one of a beginning and an end of the vector element;
wherein identifying the high bit indicator defines at least one of a corresponding beginning point and an end point of an operation to be performed on data of the vector element stored in a row of memory cells.
7. The method of claim 1 , wherein the method further comprises the mask pattern defining at least one of a beginning point and an end point of a sequential arithmetical operation to be performed on data stored in a row of memory cells by generating a plurality of vector elements in the mask pattern.
8. The method of claim 1 , wherein the method further comprises performing the set including the plurality of different operations by a selected number of logical operations and shift operations performed to generate a repeating mask pattern that defines the vector element.
9. The method of claim 1 , wherein the method further comprises performing the set including the plurality of different operations on the respective plurality of data units using sensing circuitry on pitch with memory cells of a row and selectably coupled to the memory cells of the row in which the single seed vector is stored.
10. The method of claim 1 , wherein the method further comprises storing the plurality of data units of the single seed vector in a selected row of a subarray.
11. The method of claim 10 , wherein the method further comprises:
moving the plurality of data units from the selected row to a sensing component stripe on pitch with and selectably coupled to sense lines of the selected row; and
performing the set including the plurality of different operations on the respective plurality of data units using the sensing component stripe;
wherein the sensing component stripe comprises a sense amplifier and a compute component.
12. The method of claim 1 , wherein the method further comprises:
storing the plurality of data units of the single seed vector in a sensing component stripe on pitch with and selectably coupled to sense lines of a selectable subarray; and
performing the set including the plurality of different operations on the respective plurality of data units using the sensing component stripe;
wherein the sensing component stripe comprises a sense amplifier and a compute component.
13. A method, comprising:
generating a mask pattern including a plurality of data units using a set including a plurality of different operations performed on a plurality of data units of a single seed vector having a predetermined data unit at each bit position, wherein the single seed vector includes a continuous series of the data units on which the set including the plurality of different operations is performed to generate a plurality of mask patterns having different bit interval lengths of vector elements; and
identifying a high bit indicator associated with at least one of a beginning and an end of a vector element to reduce a probability of continued performance of an operation into data units not in an intended bit interval length of the vector element;
wherein the generated mask pattern is selected from a plurality of different mask patterns defined as being generated by performance of a corresponding plurality of sets including a plurality of different operations on the respective plurality of data units of the single seed vector.
14. The method of claim 13 , wherein the method further comprises:
generating a different bit interval length of a vector element in each different mask pattern by performing a corresponding set including a plurality of different operations on the respective plurality of data units;
wherein the corresponding set including the plurality of different operations is selectable from the plurality of sets including a plurality of different operations to generate the different bit interval length of the vector element in a particular mask pattern.
15. The method of claim 13 , wherein the method further comprises:
performing the corresponding plurality of sets including the plurality of different operations by performing different sequences of operations selected from AND, AND NOT, and SHIFT operations;
wherein each sequence of operations generates a repeating mask pattern having a bit interval length for a vector element different from a bit interval length generated by performance of other selectable sequences of operations.
16. The method of claim 13 , wherein the method further comprises:
storing a generated mask pattern having a plurality of vector elements; and
defining, by comparison to the generated mask pattern, at least one of beginning points and end points of a sequence including a plurality of different operations to be performed on data stored in a row of the memory cells.
17. The method of claim 13 , wherein the method further comprises:
forming the single seed vector as a plurality of adjacent sequences of a same number of a plurality of data units;
wherein at least one data unit in a first sequence differs from a data unit at a corresponding position in an adjacent second sequence.
18. The method of claim 13 , wherein the method further comprises:
forming the single seed vector as a plurality of adjacent sequences of a plurality of data units;
wherein each of the plurality of data units in the adjacent sequences is a multiple of 64 data units.
19. The method of claim 13 , wherein the method further comprises performing the set including the plurality of different operations on pitch with a plurality of memory cells in a memory device.
20. The method of claim 13 , wherein the method further comprises loading, in a computing system, the single seed vector at system boot or program start for generation of the mask pattern.
21. A method, comprising:
performing a set including a plurality of different operations on data units at corresponding positions in sequences of a plurality of seed vectors using a selected number of logical operations and shift operations, wherein each of the respective the seed vectors includes a single seed vector as a continuous series of the data units having a predetermined data unit at each bit position on which the set including the plurality of different operations is performed to generate a plurality of mask patterns having different bit interval lengths of vector elements; and
generating a repeating mask pattern that defines a plurality of vector elements, wherein each of the vector elements includes a plurality of data units.
22. The method of claim 21 , wherein the method further comprises:
selecting the plurality of seed vectors from a larger plurality of selectable seed vectors to generate an intended mask pattern from a plurality of different selectable mask patterns;
wherein the plurality of different selectable mask patterns is defined as being generated by performance of a corresponding plurality of sets including the plurality of different operations on selectable pluralities of the respective larger plurality of selectable seed vectors.
23. An apparatus, comprising:
an array of memory cells configured to store a single seed vector having a predetermined data unit at each bit position, wherein the single seed vector includes a continuous series of the data units on which a set including a plurality of different operations is performed to generate a plurality of mask patterns having different bit interval lengths of vector elements that each includes a plurality of data units;
sensing circuitry coupled to the array, the sensing circuitry including a sense amplifier and a compute component coupled to a respective sense line; and
a controller configured to control the sensing circuitry and/or the array to perform the set including the plurality of different operations on the single seed vector to generate a vector element in a repeating mask pattern.
24. The apparatus of claim 23 , wherein the set including the plurality of different operations comprises a selected number of logical operations and shift operations.
25. The apparatus of claim 23 , wherein the set including the plurality of different operations comprises AND, AND NOT, and SHIFT operations performed using the sensing circuitry.
26. The apparatus of claim 23 , wherein the sensing circuitry is further configured to perform AND, AND NOT, and SHIFT operations without a sense line address access and without transferring data via an input/output (I/O) line.
27. The apparatus of claim 23 , wherein the set including the plurality of different operations is performed on a plurality of data units of the single seed vector using the sensing circuitry selectably coupled to a row in a subarray in which the single seed vector is stored.
28. The apparatus of claim 23 , wherein the apparatus further comprises a hardware pattern generator to create the single seed vector to generate an intended pattern in a mask by performance of the set including the plurality of different operations on a plurality of data units of the single seed vector.
29. The apparatus of claim 23 , wherein the sensing circuitry is further configured to store a mask having the repeating mask pattern that defines a plurality of vector elements.
30. An apparatus, comprising:
an array of memory cells configured to store a single seed vector comprising a plurality of data units having a predetermined data unit at each bit position, wherein the single seed vector includes a continuous series of the data units on which a set including a plurality of different operations is performed to generate a plurality of mask patterns having different bit interval lengths of vector elements;
a high bit indicator associated with a vector element to identify at least one of a beginning and an end of the vector element to reduce a probability of continued performance of an operation into data units not in an intended bit interval length of the vector element;
sensing circuitry coupled to the array, the sensing circuitry including a sense amplifier and a compute component coupled to a respective sense line; and
a controller configured to control the sensing circuitry and/or the array to perform the set including the plurality of different operations on the plurality of data units of the single seed vector to generate a repeating mask pattern.
31. The apparatus of claim 30 , wherein the controller is further configured to generate in the repeating mask pattern, by performance of the set including the plurality of different operations, the vector element having the high bit indicator at a bit interval.
32. The apparatus of claim 30 , wherein:
the controller is further configured to identify the high bit indicator associated with at least one of the beginning and the end of the vector element; and
the high bit indicator defines at least one of a corresponding beginning point and an end point of an operation to be performed on data of the vector element stored in a row of the memory cells.
33. The apparatus of claim 30 , wherein the controller is further configured to control:
movement to the sensing circuitry of the plurality of data units of the single seed vector from selected memory cells in which the single seed vector is stored; and
performance of the set including the plurality of different operations on the respective plurality of data units using the sensing circuitry.
34. The apparatus of claim 30 , wherein the controller is further configured to control:
generation of a different bit interval length of vector elements in different mask patterns by performance of a corresponding set including a plurality of different operations on the respective plurality of data units of the single seed vector;
wherein the corresponding set including the plurality of different operations is selectable from a plurality of sets including a plurality of different operations to generate the different bit interval length of the vector element in a particular mask pattern.
35. The apparatus of claim 30 , wherein the controller is further configured to control:
performance of a plurality of sets including a plurality of different operations, each of the respective plurality of sets having a different sequence of operations selected from a plurality of logical operations and shift operations;
wherein each sequence of operations generates a repeating mask pattern having a bit interval length for a vector element different from a bit interval length generated by performance of other selectable sequences of the operations.