Apparatuses and methods to determine timing of operations
The present disclosure includes apparatuses and methods to determine timing of operations. An example method includes performing a first operation type that uses a shared resource in a memory device. The method includes applying a scheduling policy for timing of continued performance of the first operation type based upon receipt of a request to the memory device for performance of a second operation type that uses the shared resource.
1. A method for operating a memory device, comprising:
performing a first operation type that uses a shared resource in the memory device; and
applying a scheduling policy for timing of continued performance of the first operation type based upon receipt of a request to the memory device for performance of a second operation type that uses the shared resource; wherein:
the first operation type comprises a computation operation performed between at least two data values retrieved from a number of memory arrays; and
the second operation type comprises a memory operation performed as a read operation on a single data value stored in a selected memory array or a write operation performed on a single data value to be stored in a selected memory array.
2. The method of claim 1 , wherein:
performing the first operation type comprises configuring the shared resource to perform the computation operation; and
performing the second operation type comprises configuring the shared resource to perform the memory operation; and
wherein the shared resource comprises a sense amplifier configured to be used in performance of both the first operation type and the second operation type.
3. The method of claim 1 , wherein applying the scheduling policy to the shared resource comprises providing a conflict free usage of the shared resource by the first operation type and the second operation type.
4. The method of claim 1 , wherein
applying the scheduling policy comprises applying a priority to a request to the memory device for the memory read or write operation over continued performance of the computation operation.
5. The method of claim 1 , wherein:
performing the first operation type comprises performing a sequence of sub-operations; and
performing the sub-operations of the sequence is interruptible between the sub-operations to interleave performance of the second operation type.
6. The method of claim 1 , wherein the method further comprises:
performing the first operation type using a sense amplifier and a compute component in sensing circuitry of the shared resource;
performing the second operation type using the sense amplifier and not the compute component in the sensing circuitry of the shared resource; and
using the sense amplifier of the shared resource substantially simultaneously is a potential conflict between performing the first operation type and performing the second operation type.
7. The method of claim 1 , wherein the method further comprises receiving a data value to sensing circuitry to enable performance of a sub-operation in a sequence of sub-operations for the first operation type.
8. The method of claim 7 , wherein the method further comprises:
determining that no request is pending for performance of the second operation type; and
maintaining the data value in the sensing circuitry between performance of a first sub-operation and performance of a second sub-operation in the sequence.
9. The method of claim 7 , wherein the method further comprises:
determining that a request is pending for performance of the second operation type; and
erasing the data value between performance of a first sub-operation and a second sub-operation in the sequence.
10. An apparatus, comprising:
a memory array;
sensing circuitry coupled to the array, the sensing circuitry including a sense amplifier and a compute component coupled to a respective sense line and configured to perform computation operations and memory read and write operations; and
timing circuitry coupled to the array and sensing circuitry, wherein the timing circuitry is configured to provide conflict free timing for the computation operations and memory operations on the sensing circuitry; wherein:
the computation operation is performed, between at least two data values retrieved from the array via the sense line, using the sense amplifier and the compute component;
the memory read operation is performed using the sense amplifier on a single data value stored in the array; and
the memory write operation is performed using the sense amplifier for storage of a single data value in the array.
11. The apparatus of claim 10 , wherein the timing circuitry comprises:
logic configured to:
receive a request for the computation operation;
execute coded instructions to initiate performance of the computation operation;
receive a request for the memory read or write operation; and
apply a scheduling policy to schedule performance of the computation operation and the memory read or write operation.
12. The apparatus of claim 10 , wherein the timing circuitry comprises:
logic configured to:
apply a scheduling policy by execution of coded instructions to continue performance of the initiated computation operation based upon a determination of no pending memory request.
13. The apparatus of claim 10 , wherein the timing circuitry comprises:
logic configured to operate on coded instructions to:
erase a data value stored in the sensing circuitry between performance of a first sub-operation and a second sub-operation in a sequence of computation sub-operations; and
override erasure of the data value based upon a determination of no pending memory request; and
wherein the data value remains in the sensing circuitry for performance of the second sub-operation.
14. The apparatus of claim 10 , wherein the timing circuitry comprises:
logic configured to operate on coded instructions to:
erase a data value stored in the sensing circuitry at a selectable time interval during performance of a sequence of computation sub-operations; and
override erasure of the data value at the selectable time interval based upon a determination of no pending memory request; and
wherein the data value remains in the sensing circuitry for performance of the sequence of computation sub-operations.
15. The apparatus of claim 10 , wherein the apparatus further comprises:
a sequencer that comprises a state machine configured to:
retrieve coded instructions; and
sequence the computation operations.
16. The apparatus of claim 10 , wherein the computation operations comprise logical AND, OR, and XOR operations performed using the sensing circuitry.
17. The apparatus of claim 10 , wherein:
an initiated computation operation is a sequence of computation sub-operations; and
a scheduling policy operates on coded instructions to interrupt performance of the sequence of computation sub-operations between the sub-operations for performance of a pending memory operation.
18. The apparatus of claim 10 , wherein:
the array is a processing in memory (PIM) dynamic random access memory (DRAM) array;
the computation operations are PIM operations performed using the sense amplifier and the compute component of the sensing circuitry coupled via the sense line to the array; and
the memory operations are DRAM operations performed using the sense amplifier and without using the compute component of the respective sensing circuitry.