Overlaying of clock and data propagation in emulation
A computer-implemented method for configuring a hardware verification system is presented. The method includes receiving a first data representative of a first design including a first sequential element configured to be evaluated in accordance with a first signal. The method further includes transforming the first data into a second data representative of a second design. The second data includes a third data associated with a second sequential element including functionality of the first sequential element and a fourth data associated with a first logic circuit. The evaluation of the second sequential element at cycle i of the hardware verification system is performed in accordance with the first logic circuit and a value of the first signal as computed during cycle i−1 of the hardware verification system when the second data is compiled for programming into the hardware verification system, where i is an integer number.
1. A computer-implemented method for configuring a hardware verification system, the method comprising:
receiving, in the computer, a first data representative of a first design including a first sequential element configured to be evaluated in accordance with a first signal, when the computer is invoked to configure the verification system; and
transforming, using the computer, the first data into a second data representative of a second design, said second data including:
a third data associated with a second sequential element including functionality of the first sequential element; and
a fourth data associated with a first logic circuit,
wherein evaluation of the second sequential element at cycle i of the hardware verification system is performed in accordance with the first logic circuit and a value of the first signal as computed during cycle i−1 of the hardware verification system when the second data is compiled for programming into the hardware verification system,
wherein i is an integer number.
2. The computer-implemented method of claim 1 , wherein the second design causes a value of the first signal as computed during cycle i to be propagated to a data input terminal of the first logic circuit.
3. The computer-implemented method of claim 1 , wherein evaluation of the first logic circuit at cycle i is performed in accordance with a second signal different from the first signal before a value of the first signal as computed during cycle i is caused by the second design to be propagated to a data input terminal of the first logic circuit.
4. The computer-implemented method of claim 1 , wherein a value of a second signal different from the first signal and as computed during cycle i−1 is caused to be propagated at cycle i to a data input terminal of the second sequential element.
5. The computer-implemented method of claim 1 , wherein evaluation of the second sequential element is caused to be disabled during a cycle of the hardware verification system corresponding to a cycle of the first design that starts a plurality of cycles of the first design.
6. The computer-implemented method of claim 1 , wherein the first logic circuit includes a flip-flop evaluated in accordance with a second signal different from the first signal, the second signal being coupled to a clock input terminal of the flip-flop.
7. The computer-implemented method of claim 1 , wherein the first logic circuit includes a latch evaluated in accordance with a second signal different from the first signal, the second signal being coupled to an enable input terminal of the latch.
8. The computer-implemented method of claim 1 , wherein the second sequential element is a flip-flop having a clock input terminal coupled to an output terminal of the first logic circuit.
9. The computer-implemented method of claim 1 , wherein the second sequential element is a latch having an enable input terminal coupled to an output terminal of the first logic circuit.
10. The computer-implemented method of claim 1 , wherein the first design further includes a third sequential element configured to:
generate the first signal;
be evaluated in accordance with a second signal different from the first signal; and
receive a third signal different from the first and second signals, said third signal being coupled from a first output terminal of the first sequential element to a first data input terminal of the third sequential element,
wherein the first logic circuit at cycle i causes propagation of a value of the third signal as computed during cycle i−1 in accordance with a transition of the value of the second signal as computed asynchronously during cycle i.
11. The computer-implemented method of claim 10 , wherein the third signal consists of a data path signal.
12. The computer-implemented method of claim 10 , wherein, in the first design, the third sequential element is a flip-flop and the second signal is coupled to a clock input of the flip-flop.
13. The computer-implemented method of claim 10 , wherein, in the first design, the third sequential element is a latch and the second signal is coupled to an enable input of the latch.
14. The computer-implemented method of claim 10 , wherein the first logic circuit is caused to asynchronously select at cycle i the value of either the first signal as computed during cycle i−1 or the third signal as computed during cycle i−1 in accordance with the transition of the value of the second signal as computed asynchronously during cycle i.
15. The computer-implemented method of claim 10 , wherein the first logic circuit is caused during cycle i to asynchronously select:
at the start of cycle i the value of the first signal as computed during cycle i−1; and
before the end of cycle i the value of the third signal as computed during cycle i−1.
16. The computer-implemented method of claim 10 , wherein the second design causes a value of the second signal as computed during cycle i to be propagated to a data input terminal of the first logic circuit.
17. The computer-implemented method of claim 10 , wherein evaluation of the first logic circuit at cycle i is performed in accordance with a fourth signal different from the first, second, and third signals before a value of the second signal as computed during cycle i is caused by the second design to be propagated to a data input terminal of the first logic circuit.
18. The computer-implemented method of claim 10 , wherein the transforming causes the first logic circuit to replace the third sequential element.
19. A non-transitory computer-readable storage medium comprising instructions, which when executed by a computer, cause the computer to:
receive a first data representative of a first design including a first sequential element configured to be evaluated in accordance with a first signal, when the computer is invoked to configure the verification system; and
transform the first data into a second data representative of a second design, said second data including:
a third data associated with a second sequential element including functionality of the first sequential element; and
a fourth data associated with a first logic circuit,
wherein evaluation of the second sequential element at cycle i of the hardware verification system is performed in accordance with the first logic circuit and a value of the first signal as computed during cycle i−1 of the hardware verification system when the second data is compiled for programming into the hardware verification system,
wherein i is an integer number.
20. The non-transitory computer-readable storage medium of claim 19 , wherein the second design causes a value of the first signal as computed during cycle i to be propagated to a data input terminal of the first logic circuit.
21. The non-transitory computer-readable storage medium of claim 19 , wherein evaluation of the first logic circuit at cycle i is performed in accordance with a second signal different from the first signal before a value of the first signal as computed during cycle I is caused by the second design to be propagated to a data input terminal of the first logic circuit.
22. The non-transitory computer-readable storage medium of claim 19 , wherein a value of a second signal different from the first signal and as computed during cycle i−1 is caused to be propagated at cycle i to a data input terminal of the second sequential element.
23. The non-transitory computer-readable storage medium of claim 19 , wherein evaluation of the second sequential element is caused to be disabled during a cycle of the hardware verification system corresponding to a cycle of the first design that starts a plurality of cycles of the first design.
24. The non-transitory computer-readable storage medium of claim 19 , wherein the first logic circuit includes a flip-flop evaluated in accordance with a second signal different from the first signal, the second signal being coupled to a clock input terminal of the flip-flop.
25. The non-transitory computer-readable storage medium of claim 19 , wherein the first logic circuit includes a latch evaluated in accordance with a second signal different from the first signal, the second signal being coupled to an enable input terminal of the latch.
26. The non-transitory computer-readable storage medium of claim 19 , wherein the second sequential element is a flip-flop having a clock input terminal coupled to an output terminal of the first logic circuit.
27. The non-transitory computer-readable storage medium of claim 19 , wherein the second sequential element is a latch having an enable input terminal coupled to an output terminal of the first logic circuit.
28. The non-transitory computer-readable storage medium of claim 19 , wherein the first design further includes a third sequential element configured to:
generate the first signal;
be evaluated in accordance with a second signal different from the first signal; and
receive a third signal different from the first and second signals, said third signal being coupled from a first output terminal of the first sequential element to a first data input terminal of the third sequential element,
wherein the first logic circuit at cycle i causes propagation of a value of the third signal as computed during cycle i−1 in accordance with a transition of the value of the second signal as computed asynchronously during cycle i.
29. The non-transitory computer-readable storage medium of claim 28 , wherein the third signal consists of a data path signal.
30. The non-transitory computer-readable storage medium of claim 28 , wherein, in the first design, the third sequential element is a flip-flop and the second signal is coupled to a clock input of the flip-flop.
31. The non-transitory computer-readable storage medium of claim 28 , wherein, in the first design, the third sequential element is a latch and the second signal is coupled to an enable input of the latch.
32. The non-transitory computer-readable storage medium of claim 28 , wherein the first logic circuit is caused to asynchronously select at cycle i the value of either the first signal as computed during cycle i−1 or the third signal as computed during cycle i−1 in accordance with the transition of the value of the second signal as computed asynchronously during cycle i.
33. The non-transitory computer-readable storage medium of claim 28 , wherein the first logic circuit is caused during cycle i to asynchronously select:
at the start of cycle i the value of the first signal as computed during cycle i−1; and
before the end of cycle i the value of the third signal as computed during cycle i−1.
34. The non-transitory computer-readable storage medium of claim 28 , wherein the second design causes a value of the second signal as computed during cycle i to be propagated to a data input terminal of the first logic circuit.
35. The non-transitory computer-readable storage medium of claim 28 , wherein evaluation of the first logic circuit at cycle i is performed in accordance with a fourth signal different from the first, second, and third signals before a value of the second signal as computed during cycle i is caused by the second design to be propagated to a data input terminal of the first logic circuit.
36. The non-transitory computer-readable storage medium of claim 28 , wherein the transforming causes the first logic circuit to replace the third sequential element.
37. A computer system operative to:
receive a first data representative of a first design including a first sequential element configured to be evaluated in accordance with a first signal, when the computer is invoked to configure a hardware verification of the first design; and
transform the first data into a second data representative of a second design, said second data including:
a third data associated with a second sequential element including functionality of the first sequential element; and
a fourth data associated with a first logic circuit,
wherein evaluation of the second sequential element at cycle i of the hardware verification system is performed in accordance with the first logic circuit and a value of the first signal as computed during cycle i−1 of the hardware verification system when the second data is compiled for programming into the hardware verification system,
wherein i is an integer number.
38. The computer system of claim 37 , wherein the second design causes a value of the first signal as computed during cycle i to be propagated to a data input terminal of the first logic circuit.
39. The computer system of claim 37 , wherein evaluation of the first logic circuit at cycle i is performed in accordance with a second signal different from the first signal before a value of the first signal as computed during cycle i is caused by the second design to be propagated to a data input terminal of the first logic circuit.
40. The computer system of claim 37 , wherein a value of a second signal different from the first signal and as computed during cycle i−1 is caused to be propagated at cycle i to a data input terminal of the second sequential element.
41. The computer system of claim 37 , wherein evaluation of the second sequential element is caused to be disabled during a cycle of the hardware verification system corresponding to a cycle of the first design that starts a plurality of cycles of the first design.
42. The computer system of claim 37 , wherein the first logic circuit includes a flip-flop evaluated in accordance with a second signal different from the first signal, the second signal being coupled to a clock input terminal of the flip-flop.
43. The computer system of claim 37 , wherein the first logic circuit includes a latch evaluated in accordance with a second signal different from the first signal, the second signal being coupled to an enable input terminal of the latch.
44. The computer system of claim 37 , wherein the second sequential element is a flip-flop having a clock input terminal coupled to an output terminal of the first logic circuit.
45. The computer system of claim 37 , wherein the second sequential element is a latch having an enable input terminal coupled to an output terminal of the first logic circuit.
46. The computer system of claim 37 , wherein the first design further includes a third sequential element configured to:
generate the first signal;
be evaluated in accordance with a second signal different from the first signal; and
receive a third signal different from the first and second signals, said third signal being coupled from a first output terminal of the first sequential element to a first data input terminal of the third sequential element,
wherein the first logic circuit at cycle i causes propagation of a value of the third signal as computed during cycle i−1 in accordance with a transition of the value of the second signal as computed asynchronously during cycle i.
47. The computer system of claim 46 , wherein the third signal consists of a data path signal.
48. The computer system of claim 46 , wherein, in the first design, the third sequential element is a flip-flop and the second signal is coupled to a clock input of the flip-flop.
49. The computer system of claim 46 , wherein, in the first design, the third sequential element is a latch and the second signal is coupled to an enable input of the latch.
50. The computer system of claim 46 , wherein the first logic circuit is caused to asynchronously select at cycle i the value of either the first signal as computed during cycle i−1 or the third signal as computed during cycle i−1 in accordance with the transition of the value of the second signal as computed asynchronously during cycle i.
51. The computer system of claim 46 , wherein the first logic circuit is caused during cycle i to asynchronously select:
at the start of cycle i the value of the first signal as computed during cycle i−1; and
before the end of cycle i the value of the third signal as computed during cycle i−1.
52. The computer system of claim 46 , wherein the second design causes a value of the second signal as computed during cycle i to be propagated to a data input terminal of the first logic circuit.
53. The computer system of claim 46 , wherein evaluation of the first logic circuit at cycle i is performed in accordance with a fourth signal different from the first, second, and third signals before a value of the second signal as computed during cycle i is caused by the second design to be propagated to a data input terminal of the first logic circuit.
54. The computer system of claim 46 , wherein the transforming causes the first logic circuit to replace the third sequential element.