Memory devices including dynamic superblocks, and related methods and electronic systems
View Patent ↗A memory device includes a memory array having non-volatile memory cells, and a memory controller configured to dynamically construct a superblock during each garbage collection process based, at least in part, on an amount of valid data present in each physical block of the memory array. Another memory device includes physical blocks of memory cells and a memory controller configured to construct a new superblock dynamically each time garbage collection occurs for the physical blocks regardless of whether any physical blocks are determined to be bad. Additional methods for managing operation of a memory device and related electronic systems are also described.
1. A memory device, comprising:
a memory array comprising a number of dies; and
a memory controller operably coupled to the memory array, the memory controller configured to:
determine an amount of valid data in each of:
first physical blocks of a first die of the number of dies;
second physical blocks of a second die of the number of dies;
third physical blocks of a third die of the number of dies; and
fourth physical blocks of a fourth die of the number of dies, the first and second dies managed by a first channel of the memory controller and the third die and fourth die managed by a second channel of the memory controller, a channel comprising a hardware unit that enables the memory controller to communicate with a set of dies at the same time; and
dynamically construct a superblock for at least one garbage collection process by selecting at least two physical blocks from the first channel that have a lowest amount of valid data and a second lowest amount of data relative to other physical blocks of the first channel and selecting at least two physical blocks from the second channel that have a lowest amount of valid data and a second lowest amount of valid data relative to other physical blocks of the second channel, the superblock dynamically constructed in a manner that is different than a manner with which superblocks are constructed for reading and writing data, and based, at least in part, on an amount of valid data present in each physical block of the memory array and not a determination of bad physical blocks when constructing the superblock for the at least one garbage collection process.
2. The memory device of claim 1 , wherein the memory controller includes a flash translation layer configured to perform garbage collection and address mapping for the memory controller.
3. The memory device of claim 1 , wherein the memory controller is further configured to construct the superblock by selecting multiple physical blocks from one or more of the first die or the second die, and selecting multiple physical blocks from one or more of the third die or the fourth die.
4. The memory device of claim 1 , wherein the memory controller is further configured to dynamically determine a size for the superblock for the at least one garbage collection process based, at least in part, on a number of physical blocks needed to be cleared during a given garbage collection process.
5. The memory device of claim 4 , wherein the memory controller is configured to construct a first superblock according to a first set of rules during a first garbage collection process, and a second superblock according to a second set of rules during a second garbage collection process.
6. The memory device of claim 1 , the memory array having non-volatile memory cells configured as at least one of NAND Flash, NOR Flash, erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), ferroelectric RAM (FRAM), or magnetoresistive RAM (MRAM).
7. A memory device, comprising:
physical blocks of memory cells; and
a memory controller configured to dynamically construct a new superblock each time garbage collection occurs for the physical blocks regardless of whether any physical blocks are determined to be bad and different than construction of superblocks used during reading and writing, the new superblock dynamically constructed using at least two physical blocks from a die of a number of dies managed by the memory controller via a channel, and at least two additional physical blocks from another die of an additional number of dies managed by the memory controller via another channel, wherein a channel comprises a hardware unit that enables the memory controller to communicate with a set of dies at the same time.
8. The memory device of claim 7 , wherein the memory controller is configured to execute firmware having an application layer, a file system layer, and a translation layer.
9. The memory device of claim 8 , wherein the translation layer includes a Flash Translation Layer (FTL) configured to construct the new superblock and perform the garbage collection.
10. The memory device of claim 9 , wherein the FTL is configured to construct the new superblock responsive to determining the at least one physical block and the at least one additional physical block have a minimum total amount of valid data.
11. The memory device of claim 10 , wherein the at least one physical block includes at least some physical blocks from different dies that comprise the memory cells.
12. The memory device of claim 10 , wherein the at least one physical block includes at least some physical blocks from a common die that comprise the memory cells.
13. A method for managing operation of a memory device, the method comprising:
initiating a garbage collection process for a memory array divided into physical blocks of data;
determining an amount of valid data for the physical blocks of data; and
constructing a dynamic superblock via linking at least one physical block of each of a first die and a second die for a first channel with at least one physical block of each of a third die and a fourth die for a second channel, a channel comprising a hardware unit that enables a memory controller to communicate with a set of dies at the same time, the dynamic superblock constructed different than construction of superblocks used during reading and writing and based, at least in part, on the amount of valid data for the physical blocks of data for the memory array at a time of constructing the dynamic superblock for the garbage collection process and not responsive to a determination of physical blocks to be bad.
14. The method of claim 13 , further comprising:
moving valid data for physical blocks selected for construction of the dynamic superblock; and
erasing the physical blocks selected for construction of the dynamic superblock.
15. The method of claim 13 , wherein initiating the garbage collection process includes:
separating and recovering valid data from invalid data for the physical blocks of the dynamic superblock;
re-distributing the valid data into a pool of available physical blocks outside of the dynamic superblock; and
erasing the physical blocks of the dynamic superblock to free up space therein for additional writes to occur.
16. The method of claim 13 , wherein determining the amount of valid data for the physical blocks of data includes:
searching through physical blocks for each die managed by the first channel to determine valid data for each physical block of the first channel; and
searching through physical blocks for each die managed by the second channel to determine valid data for each physical block of the second channel.
17. The method of claim 13 , wherein linking at least one physical block of each of the first die and the second die for the first channel with at least one physical block of each of the third die and the fourth die for the second channel includes:
selecting the at least one physical block of each of the first die and the second die for the first channel having a minimum amount of valid data among the physical blocks for the first channel; and
selecting the at least one physical block of each of the third die and the fourth die for the second channel having a minimum amount of valid data among the physical blocks for the second channel.
18. An electronic system, comprising:
a memory device including dies having physical blocks, the memory device configured to link a first set of at least two physical blocks from at least two different dies managed via a first channel and a second set of at least three physical blocks from at least two different dies managed via a second channel to dynamically construct a superblock responsive to a garbage collection process in a manner that is different than construction of superblocks used for reading and writing data before and after the second garbage collection process, a channel comprising a hardware unit that enables the memory device to communicate with a set of dies at the same time.
19. The electronic system of claim 18 , further comprising at least one of an embedded multi-media controller (eMMC), a Solid State Drive (SSD), or a Universal Flash Storage (UFS) devices that includes the memory device.
20. The electronic system of claim 18 , further comprising at least one processor coupled to the memory device, at least one input device coupled to the processor, and at least one output device coupled to the processor.
21. The electronic system of claim 18 , wherein the first set of at least three physical blocks includes at least two physical blocks from the same die.