MOS capacitors with interleaved fingers and methods of forming the same
A capacitor structure is described. The capacitor structure includes a substrate; a plurality of source/drain regions formed in said substrate to form an active area, the active area having an active area width; and a first and a second plurality of gates formed above the substrate. Each gate of the first and second plurality of gates having a gate width. The gate width is configured to be less than the active area width and each gate of the first and second plurality of gates is formed between a pair of source/drain regions of the plurality of source/drain regions such that the first plurality of gates interleave with the second plurality of gates.
1. A capacitor structure comprising:
a substrate;
a plurality of source/drain regions formed in said substrate to form an active area, the active area having an active area width;
a first plurality of gates formed above said substrate, each gate of said first plurality of gates having a first gate width, said first gate width configured to be less than said active area width, each gate of said first plurality of gates formed between a pair of source/drain regions of said plurality of source/drain regions; and
a second plurality of gates formed above said substrate, each gate of said second plurality of gates having a second gate width, said second gate width configured to be less than said active area width, each gate of said second plurality of gates formed between a pair of source/drain regions of said plurality of source drain regions such that said first plurality of gates interleave with said second plurality of gates.
2. The capacitor structure of claim 1 , wherein said substrate is an silicon-on-insulator substrate.
3. The capacitor structure of claim 1 , wherein said plurality of source/drain regions, said first plurality of gates, and said second plurality of gates are interconnected to form one or more pairs of capacitors connected in an anti-series configuration.
4. The capacitor structure of claim 1 , wherein said plurality of source/drain regions, said first plurality of gates, and said second plurality of gates are interconnected to form a variable capacitor cell of a variable capacitor array.
5. The capacitor structure of claim 4 , wherein the variable capacitor cell is part of an integrated circuit.
6. The capacitor structure of claim 1 , wherein said plurality of source/drain regions, said first plurality of gates, and said second plurality of gates are interconnected to form a plurality of variable capacitor cells of a variable capacitor array.
7. A method to form a plurality of capacitors comprising:
forming a plurality of source/drain regions in said substrate to form an active area, the active area having an active area width;
forming a first plurality of gates above said substrate, each gate of said first plurality of gates having a first gate width, said first gate width configured to be less than said active area width, each gate of said first plurality of gates formed between a pair of source/drain regions of said plurality of source/drain regions; and
forming second plurality of gates above said substrate, each gate of said second plurality of gates having a second gate width, said second gate width configured to be less than said active area width, each gate of said second plurality of gates formed between a pair of source/drain regions of said plurality of source drain regions such that said first plurality of gates interleave with said second plurality of gates.
8. The method of claim 7 , wherein said substrate is an silicon-on-insulator substrate.
9. The method of claim 7 , further comprising forming connections between said plurality of source/drain regions, said first plurality of gates, and said second plurality of gates to form one or more pairs of capacitors connected in an anti-series configuration.
10. The method of claim 7 , further comprising forming connections between said plurality of source/drain regions, said first plurality of gates, and said second plurality of gates to form a variable capacitor cell of a variable capacitor array.
11. The method of claim 7 , further comprising forming connections between said plurality of source/drain regions, first plurality of gates, and said second plurality of gates to form a plurality of variable capacitor cells of a variable capacitor array.
12. An integrated circuit comprising:
a substrate;
a plurality of source/drain regions formed in said substrate to form an active area, the active area having an active area width;
a first plurality of gates formed above said substrate, each gate of said first plurality of gates having a first gate width, said first gate width configured to be less than said active area width, each gate of said first plurality of gates formed between a pair of source/drain regions of said plurality of source/drain regions; and
a second plurality of gates formed above said substrate, each gate of said second plurality of gates having a second gate width, said second gate width configured to be less than said active area width, each gate of said second plurality of gates formed between a pair of source/drain regions of said plurality of source drain regions such that said first plurality of gates interleave with said second plurality of gates.
13. The integrated circuit of claim 12 , wherein said substrate is a silicon-on-insulator substrate.
14. The integrated circuit of claim 12 , wherein said plurality of source/drain regions, said first plurality of gates, and said second plurality of gates are interconnected to form one or more pairs of capacitors connected in an anti-series configuration.
15. The integrated circuit of claim 12 , wherein said plurality of source/drain regions, said first plurality of gates, and said second plurality of gates are interconnected to form a variable capacitor cell of a variable capacitor array.
16. The integrated circuit of claim 12 , wherein said plurality of source/drain regions, first plurality of gates, and said second plurality of gates are interconnected to form a plurality of variable capacitor cells of a variable capacitor array.
17. The integrated circuit of claim 12 , further comprising a bias voltage generator configured to generate a bias voltage for each one of said plurality of variable capacitor cells of said variable capacitor array.
18. The integrated circuit of claim 17 , further comprising an interface configured to receive a control signal for said bias voltage generator used to adjust a value of said bias voltage for each one of said plurality of variable capacitor cells of said variable capacitor array.
19. The integrated circuit of claim 18 , wherein said interface is a Mobile Industry Processor Interface radio front end interface.
20. The integrated circuit of claim 12 , wherein said plurality of source/drain regions, first plurality of gates, and said second plurality of gates are interconnected to form a plurality of variable capacitor arrays.