Implementation of VMCO area switching cell to VBL architecture
Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array.
1. A method for fabricating a portion of a memory array, comprising:
forming an alternating stack of word line layers and dielectric layers, the alternating stack of word line layers and dielectric layers includes a first dielectric layer arranged above a first word line layer;
etching a memory hole extending through the first dielectric layer and the first word line layer;
recessing a portion of the first word line layer arranged below a portion of the first dielectric layer subsequent to etching the memory hole;
depositing a layer of amorphous silicon within a first region of the recessed portion of the first word line layer arranged below the portion of the first dielectric layer;
depositing a layer of titanium oxide within a second region of the recessed portion of the first word line layer arranged below the portion of the first dielectric layer; and
filling at least a portion of the memory hole with a conducting material subsequent to depositing the layer of amorphous silicon and the layer of titanium oxide.
2. The method of claim 1 , wherein:
the alternating stack of word line layers and dielectric layers includes a second word line layer arranged below the first word line layer, the etching the memory hole includes etching through the first word line layer and the second word line layer; and
the recessing the portion of the first word line layer includes laterally recessing the portion of the first word line layer.
3. The method of claim 1 , wherein:
the depositing the layer of amorphous silicon is performed subsequent to the depositing the layer of titanium oxide.
4. The method of claim 1 , wherein:
the layer of amorphous silicon is arranged between the layer of titanium oxide and the conducting material.
5. The method of claim 1 , wherein:
the layer of titanium oxide is arranged between the layer of amorphous silicon and the conducting material.
6. The method of claim 1 , wherein:
the word line layers comprise a word line material;
the dielectric layers comprise a dielectric material; and
the recessing the portion of the first word line layer includes performing an etching process that removes the word line material while being highly selective to the dielectric material.
7. The method of claim 1 , wherein:
the recessed portion of the first word line layer is completely filled by the layer of amorphous silicon and the layer of titanium oxide; and
the layer of amorphous silicon and the layer of titanium oxide do not extend into the memory hole.
8. The method of claim 1 , further comprising:
depositing one of a layer of titanium metal or a layer of aluminum oxide between the layer of titanium oxide and the layer of amorphous silicon.
9. The method of claim 1 , wherein:
the word line layers comprise titanium nitride; and
the dielectric layers comprise silicon dioxide.
10. The method of claim 1 , wherein:
the etching the memory hole includes etching the memory hole extending through two or more word line layers of the alternating stack of word line layers and dielectric layers; and
the recessing the portion of the first word line layer includes laterally recessing the two or more word line layers simultaneously.
11. A method, comprising:
depositing a word line material and subsequently depositing a dielectric material above the word line material;
etching a memory hole extending through the word line material and the dielectric material;
recessing a portion of the word line material arranged below a portion of the dielectric material without removing a threshold amount of the dielectric material subsequent to etching the memory hole;
depositing a layer of amorphous silicon within a first region of the recessed portion of the word line material arranged below the portion of the dielectric material;
depositing a layer of titanium oxide within a second region of the recessed portion of the word line material arranged below the portion of the dielectric material; and
filling at least a portion of the memory hole with a conducting material, the layer of amorphous silicon and the layer of titanium oxide do not extend into the memory hole.
12. The method of claim 11 , wherein:
the recessing the portion of the word line material includes laterally recessing the portion of the word line material.
13. The method of claim 11 , wherein:
the depositing the layer of amorphous silicon is performed subsequent to the depositing the layer of titanium oxide.
14. The method of claim 11 , wherein:
the layer of amorphous silicon is arranged between the layer of titanium oxide and the conducting material.
15. The method of claim 11 , wherein:
the recessed portion of the word line material is completely filled by the layer of amorphous silicon and the layer of titanium oxide.
16. The method of claim 11 , further comprising:
depositing one of a layer of titanium metal or a layer of aluminum oxide between the layer of titanium oxide and the layer of amorphous silicon.
17. The method of claim 11 , wherein:
the conducting material comprises tungsten;
the word line material comprises titanium nitride; and
the dielectric material comprises silicon dioxide.
18. The method of claim 11 , wherein:
the etching the memory hole includes etching the memory hole extending through two or more word line layers; and
the recessing the portion of the word line material includes laterally recessing the two or more word line layers simultaneously.