IP Library › Granted Patent US 10,073,482
Granted Patent B2
US 10,073,482 · App. 15/085,863 · Granted Sep 11, 2018

Apparatus and methods for MOS capacitor structures for variable capacitor arrays

Inventors: Rien Gahlsdorf (Bedford, NH); Jianwen Bao (Greensboro, NC)
Assignee: TDK Corporation
G05F3/24G05F3/205H01L27/0811H01L27/1203H01L29/66189H01L29/94H01L29/93
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Quick Facts
Patent No.
US 10,073,482
App. No.
15/085,863
Granted
Sep 11, 2018
Kind
B2
Abstract

A capacitor structure is described. A capacitor structure including a substrate and at least one device formed on the substrate. The device including first and second sections. Each of the first and second sections including a plurality of source/drain regions formed in the substrate and a plurality of gates formed above the substrate such that each of the plurality of gates is formed between each pair of source/drain regions to form a section channel between each pair of source/drain regions. The plurality of gates of the first and second sections are coupled with each other.

Claims (55)

1. A capacitor structure comprising:

a substrate; and

at least one capacitor formed on said substrate, each capacitor including a first section and a second section, said first section including:

a first plurality of source/drain regions formed in said substrate, and

a first plurality of gates formed above said substrate such that each of said first plurality of gates is formed between each pair of source/drain regions of said first plurality of source/drain regions to form a first section channel between said each pair of source/drain regions, each source/drain region formed between a pair of gates of the first plurality of gates is a source for a first gate of said pair of gates and a drain for a second gate of said pair of gates,

said second section including:

a second plurality of source/drain regions formed in said substrate, and

a second plurality of gates formed above said substrate such that each of said second plurality of gates is formed between each pair of source/drain regions of said second plurality of source/drain regions to form a second section channel between said each pair of source/drain regions, each source/drain region formed between a pair of gates of the second plurality of gates is a source for a first gate of said pair of gates and a drain for a second gate of said pair of gates,

wherein said first plurality of gates are coupled with said second plurality of gates.

2. The capacitor structure of claim 1 , wherein said substrate is a silicon-on-insulator substrate.

3. The capacitor structure of claim 1 , wherein said substrate includes at least a second capacitor including a third section and a fourth section, said third section including a third plurality of source/drain regions formed in said substrate and a third plurality of gates formed above said substrate such that each of said third plurality of gates is formed between each pair of source/drain regions of said third plurality of source/drain regions to form a third section channel between said each pair of source/drain regions, said fourth section including a fourth plurality of source/drain regions and a fourth plurality of gates formed above said substrate such that each of said fourth plurality of gates is formed between each pair of source/drain regions of said fourth plurality of source/drain regions to form a fourth section channel between said each pair of source/drain regions, said first section, said second section, said third section, and said fourth section are interconnected to form a pair of capacitors connected in an anti-series configuration.

4. The capacitor structure of claim 1 , wherein said substrate includes at least a second capacitor including a third section and a fourth section, said third section including a third plurality of source/drain regions formed in said substrate and a third plurality of gates formed above said substrate such that each of said third plurality of gates is formed between each pair of source/drain regions of said third plurality of source/drain regions to form a third section channel between said each pair of source/drain regions, said fourth section including a fourth plurality of source/drain regions and a fourth plurality of gates formed above said substrate such that each of said fourth plurality of gates is formed between each pair of source/drain regions of said fourth plurality of source/drain regions to form a fourth section channel between said each pair of source/drain regions, said first section, said second section, said third section, and said fourth section are interconnected to form a variable capacitor cell of a variable capacitor array.

5. The capacitor structure of claim 4 , wherein the variable capacitor cell is part of an integrated circuit.

6. The capacitor structure of claim 1 , wherein said substrate includes at least a second capacitor including a third section and a fourth section, said third section including a third plurality of source/drain regions formed in said substrate and a third plurality of gates formed above said substrate such that each of said third plurality of gates is formed between each pair of source/drain regions of said third plurality of source/drain regions to form a third section channel between said each pair of source/drain regions, said fourth section including a fourth plurality of source/drain regions and a fourth plurality of gates formed above said substrate such that each of said fourth plurality of gates is formed between each pair of source/drain regions of said fourth plurality of source/drain regions to form a fourth section channel between said each pair of source/drain regions, said first section, said second section, said third section, and said fourth section are interconnected to form a plurality of variable capacitor cells of a variable capacitor array.

7. A method to form a plurality of capacitors comprising:

for each capacitor of said plurality of capacitors:

forming a plurality of source/drain regions in a substrate;

forming a first plurality of gates above said substrate such that each of said first plurality of gates is formed between each pair of source/drain regions of said first plurality of source/drain regions to form a first section channel between said each pair of source/drain regions, each source/drain region formed between a pair of gates of the first plurality of gates is a source for a first gate of said pair of gates and a drain for a second gate of said pair of gates; and

forming a second plurality of gates above said substrate such that each of said second plurality of gates is formed between each pair of source/drain regions of said second plurality of source/drain regions to form a second section channel between said each pair of source/drain regions, each source/drain region formed between a pair of gates of the second plurality of gates is a source for a first gate of said pair of gates and a drain for a second gate of said pair of gates, wherein said first plurality of gates are coupled with said second plurality of gates.

8. The method of claim 7 , wherein said substrate is a silicon-on-insulator substrate.

9. The method of claim 7 , further comprising:

forming a third plurality of source/drain regions formed in said substrate;

forming a third plurality of gates formed above said substrate such that each of said third plurality of gates is formed between each pair of source/drain regions of said third plurality of source/drain regions to form a third section channel between said each pair of source/drain regions;

forming a fourth plurality of source/drain regions;

forming a fourth plurality of gates formed above said substrate such that each of said fourth plurality of gates is formed between each pair of source/drain regions of said fourth plurality of source/drain regions to form a fourth section channel between said each pair of source/drain regions; and

forming connections between said first, said second, said third and said fourth plurality of source/drain regions and said first plurality, said second plurality, said third plurality and said fourth plurality of gates to form a pair of capacitors connected in an anti-series configuration.

10. The method of claim 7 , further comprising:

forming a third plurality of source/drain regions formed in said substrate;

forming a third plurality of gates formed above said substrate such that each of said third plurality of gates is formed between each pair of source/drain regions of said third plurality of source/drain regions to form a third section channel between said each pair of source/drain regions;

forming a fourth plurality of source/drain regions;

forming a fourth plurality of gates formed above said substrate such that each of said fourth plurality of gates is formed between each pair of source/drain regions of said fourth plurality of source/drain regions to form a fourth section channel between said each pair of source/drain regions; and

forming connections between said first, said second, said third and said fourth plurality of source/drain regions and said first plurality, said second plurality, said third plurality and said fourth plurality of gates to form a variable capacitor cell of a variable capacitor array.

11. The capacitor structure of claim 7 , further comprising:

forming a third plurality of source/drain regions formed in said substrate;

forming a third plurality of gates formed above said substrate such that each of said third plurality of gates is formed between each pair of source/drain regions of said third plurality of source/drain regions to form a third section channel between said each pair of source/drain regions;

forming a fourth plurality of source/drain regions;

forming a fourth plurality of gates formed above said substrate such that each of said fourth plurality of gates is formed between each pair of source/drain regions of said fourth plurality of source/drain regions to form a fourth section channel between said each pair of source/drain regions; and

forming connections between said first, said second, said third and said fourth plurality of source/drain regions and said first plurality, said second plurality, said third plurality and said fourth plurality of gates to form a plurality of variable capacitor cells of a variable capacitor array.

12. An integrated circuit comprising:

a substrate; and

at least one capacitor formed on said substrate, each of said capacitor including a first section and a second section, said first section including:

a first plurality of source/drain regions formed in said substrate, and

a first plurality of gates formed above said substrate such that each of said first plurality of gates is formed between each pair of source/drain regions of said first plurality of source/drain regions to form a first section channel between said each pair of source/drain regions, each source/drain region formed between a pair of gates of the first plurality of gates is a source for a first gate of said pair of gates and a drain for a second gate of said pair of gates

said second section including:

a second plurality of source/drain regions formed in said substrate, and

a second plurality of gates formed above said substrate such that each of said second plurality of gates is formed between each pair of source/drain regions of said second plurality of source/drain regions to form a second section channel between said each pair of source/drain regions, each source/drain region formed between a pair of gates of the second plurality of gates is a source for a first gate of said pair of gates and a drain for a second gate of said pair of gates,

wherein said first plurality of gates are coupled with said second plurality of gates.

13. The integrated circuit of claim 12 , wherein said substrate is a silicon-on-insulator substrate.

14. The integrated circuit of claim 12 , wherein said substrate includes at least a second capacitor including a third section and a fourth section, said third section including a third plurality of source/drain regions formed in said substrate and a third plurality of gates formed above said substrate such that each of said third plurality of gates is formed between each pair of source/drain regions of said third plurality of source/drain regions to form a third section channel between said each pair of source/drain regions, said fourth section including a fourth plurality of source/drain regions and a fourth plurality of gates formed above said substrate such that each of said fourth plurality of gates is formed between each pair of source/drain regions of said fourth plurality of source/drain regions to form a fourth section channel between said each pair of source/drain regions, said first section, said second section, said third section, and said fourth section are interconnected to form a pair of capacitors connected in an anti-series configuration.

15. The integrated circuit of claim 12 , wherein said substrate includes at least a second capacitor including a third section and a fourth section, said third section including a third plurality of source/drain regions formed in said substrate and a third plurality of gates formed above said substrate such that each of said third plurality of gates is formed between each pair of source/drain regions of said third plurality of source/drain regions to form a third section channel between said each pair of source/drain regions, said fourth section including a fourth plurality of source/drain regions and a fourth plurality of gates formed above said substrate such that each of said fourth plurality of gates is formed between each pair of source/drain regions of said fourth plurality of source/drain regions to form a fourth section channel between said each pair of source/drain regions, said first section, said second section, said third section, and said fourth section are interconnected to form a variable capacitor cell of a variable capacitor array.

16. The integrated circuit of claim 12 , wherein said substrate includes at least a second capacitor including a third section and a fourth section, said third section including a third plurality of source/drain regions formed in said substrate and a third plurality of gates formed above said substrate such that each of said third plurality of gates is formed between each pair of source/drain regions of said third plurality of source/drain regions to form a third section channel between said each pair of source/drain regions, said fourth section including a fourth plurality of source/drain regions and a fourth plurality of gates formed above said substrate such that each of said fourth plurality of gates is formed between each pair of source/drain regions of said fourth plurality of source/drain regions to form a fourth section channel between said each pair of source/drain regions, said first section, said second section, said third section, and said fourth section are interconnected to form a plurality of variable capacitor cells of a variable capacitor array.

17. The integrated circuit of claim 16 , further comprising a bias voltage generator configured to generate a bias voltage for each one of said plurality of variable capacitor cells of said variable capacitor array.

18. The integrated circuit of claim 17 , further comprising an interface configured to receive a control signal for said bias voltage generator used to adjust a value of said bias voltage for each one of said plurality of variable capacitor cells of said variable capacitor array.

19. The integrated circuit of claim 18 , wherein said interface is a Mobile Industry Processor Interface radio front end interface.

20. The integrated circuit of claim 12 , wherein said substrate includes at least a second capacitor including a third section and a fourth section, said third section including a third plurality of source/drain regions formed in said substrate and a third plurality of gates formed above said substrate such that each of said third plurality of gates is formed between each pair of source/drain regions of said third plurality of source/drain regions to form a third section channel between said each pair of source/drain regions, said fourth section including a fourth plurality of source/drain regions and a fourth plurality of gates formed above said substrate such that each of said fourth plurality of gates is formed between each pair of source/drain regions of said fourth plurality of source/drain regions to form a fourth section channel between said each pair of source/drain regions, said first section, said second section, said third section, and said fourth section are interconnected to form a plurality of variable capacitor arrays.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 23, 2017
From: NEWLANS, INC.
To: TDK CORPORATION
Reel/Frame 041051/0966 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 20, 2017
From: BAO, JIM; GAHLSDORF, RIEN
To: NEWLANS, INC.
Reel/Frame 041030/0647 →
Continuity (2)
Provisional Application 62140385 · Mar 30, 2015
Related Publication 20160294369A1 · Oct 6, 2016