IP Library › Granted Patent US 10,164,656
Granted Patent B2
US 10,164,656 · App. 15/086,006 · Granted Dec 25, 2018

Bit flipping algorithm for providing soft information during hard decision hard decoding

Inventors: Tsung-Chieh Yang (Hsinchu, TW); Jian-Dong Du (Taoyuan, TW)
Assignee: Silicon Motion Inc.
H03M13/1108H03M13/1111H03M13/1125H03M13/1128H03M13/3707H03M13/3715H03M13/45
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Quick Facts
Patent No.
US 10,164,656
App. No.
15/086,006
Granted
Dec 25, 2018
Kind
B2
Abstract

A method for using a first decoder operating in a hard decision hard decoding mode to generate soft information for a second decoder operating in a hard decision soft decoding mode includes: generating a look-up table (LUT) linking a number of failed check nodes to a log-likelihood ratio (LLR) value; in a first iteration of the first decoder, inputting the number of failed check nodes to the LUT table to generate an LLR value; and outputting the LLR value to the second decoder.

Claims (9)

1. A method for performing low-density parity check (LDPC) decoding, the method comprising:

generating a look-up table (LUT) containing predetermined values linking a number of failed check nodes to a log-likelihood ratio (LLR) value;

inputting a codeword to a first decoder which operates in a hard decoding mode;

in a first iteration of the first decoder, decoding the codeword using a hard decoding algorithm to generate hard information by determining a number of failed check nodes and generating soft information by inputting the number of failed check nodes to the LUT to generate an LLR value;

performing a successive number of decoding iterations of the codeword in the first decoder using the hard decoding algorithm wherein in each iteration a number of failed check nodes is determined, and the number of failed check nodes is input to the LUT to generate an LLR value;

when a predetermined number of decoding iterations of the hard decoding algorithm is reached without parity check equations for the codeword being satisfied at check nodes, stopping decoding of the codeword using the first decoder, inputting the codeword to the second decoder and starting decoding of the codeword in the second decoder using a soft decoding algorithm and the LLR values generated by the LUT; or

when parity check equations for the codeword are satisfied at the check nodes before the predetermined number of decoding iterations of the hard decoding algorithm is reached, the decoded codeword is directly output without the second decoder being used.

2. The method of claim 1 , wherein the first decoder and the second decoder both utilize a bit flipping algorithm for decoding.

3. The method of claim 1 , wherein the LUT is generated utilizing the equation LLR_i=Max LLR*((column_weight+1−i)/column_weight+1), wherein i is a number of failed check nodes.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2017
From: YANG, TSUNG-CHIEH; DU, JIAN-DONG
To: SILICON MOTION INC.
Reel/Frame 041232/0588 →
Continuity (1)
Related Publication 20170288699A1 · Oct 5, 2017