Fabrication of vertical fin transistor with multiple threshold voltages

1. A vertical fin field effect transistor, comprising:

a first doped region in a substrate, wherein the first doped region has the same crystal orientation as the substrate;

a first portion of a vertical fin on the first doped region, wherein the first portion of the vertical fin is silicon-germanium, has the same crystal orientation as the substrate, and a first portion width;

a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin is silicon-germanium, has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width that exposes a top surface of the first portion of the vertical fin, wherein the second portion of the vertical fin has a higher germanium concentration than the first portion of a vertical fin;

a gate structure on the second portion of the vertical fin; and

a source/drain region on the top of the second portion of the vertical fin.

2. The vertical fin field effect transistor of claim 1 , wherein the source/drain region has the same crystal orientation as the vertical fin.

3. The vertical fin field effect transistor of claim 2 , which further comprises a bottom spacer between at least the drain region and the gate structure, and a top spacer between the gate structure and the source/drain region on the second portion of the vertical fin.

4. The vertical fin field effect transistor of claim 1 , wherein the second portion of the vertical fin has a germanium concentration in the range of about 20 at. % Ge to about 50 at. % Ge.

5. The vertical fin field effect transistor of claim 1 , wherein the second portion of the vertical fin has a vertically graded germanium concentration.

6. A vertical fin field effect transistor, comprising:

a first doped region in a substrate, wherein the first doped region has the same crystal orientation as the substrate;

a bottom spacer on the first doped region, wherein the bottom spacer has a top surface;

a first portion of a vertical fin on the first doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate, wherein the first portion of the vertical fin has a top surface that is at or below the top surface of the bottom spacer;

a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin extends above the top surface of the bottom spacer, wherein the width of the second portion of the vertical fin is less than the width of the first portion of the vertical fin, wherein the first portion of the vertical fin and the second portion of the vertical fin are silicon germanium, and the second portion of the vertical fin has a greater percentage of germanium than the first portion of the vertical fin;

a gate structure on the second portion of the vertical fin;

a top spacer on the gate structure; and

a source/drain region on the top of the second portion of the vertical fin.

7. The vertical fin field effect transistor of claim 6 , wherein the second portion of the vertical fin has a width in a range of about range of about 7 nm to about 18 nm, and the first portion of the vertical fin has a width in a range of about 10 nm to about 20 nm.

8. The vertical fin field effect transistor of claim 7 , wherein the second portion of the vertical fin has a germanium concentration in the range of about 20 at. % Ge to about 50 at. % Ge.

9. The vertical fin field effect transistor of claim 8 , wherein the second portion of the vertical fin has a vertically graded germanium concentration.