Micro LED display pixel architecture
A Light Emitting Diode (LED) display is described. The LED display includes a plurality of pixel circuits, each including an LED and a non-volatile memory cell to adjust current to the LED.
1. Light Emitting Diode (LED) display comprising a plurality of pixel circuits, each including:
an LED; and
a non-volatile memory cell to adjust current to the LED, wherein the current to the LED is adjusted by applying data voltages to change a threshold voltage of the non-volatile memory cell.
2. The LED display of claim 1 , wherein the pixel circuits each further comprise:
a first thin film transistor (TFT) coupled to the gate of the non-volatile memory cell to apply the data voltages; and
a second TFT coupled to the LED and the non-volatile memory cell.
3. The LED display of claim 2 , wherein the first TFT is de-activated and the second TFT is activated during a Reset pulse performed at the non-volatile memory cell.
4. The LED display of claim 3 , wherein the first TFT is activated and the second TFT is activated during a Write operation performed at the non-volatile memory cell.
5. The LED display of claim 4 , wherein the first TFT is de-activated and the second TFT is de-activated during an Emission operation performed at the non-volatile memory cell.
6. The LED display of claim 5 , wherein the non-volatile memory cell comprises a non-volatile memory cell transistor, wherein the non-volatile memory cell transistor is activated to permit current flow to the LED when activated during the Emission operation.
7. The LED display of claim 1 , wherein the non-volatile memory cell comprises:
a top gate;
a blocking oxide layer;
a charge trapping layer;
an Indium gallium zinc oxide (IGZO) layer;
a gate oxide layer; and
a bottom gate.
8. The LED display of claim 7 , wherein the charge trapping layer comprises semiconducting nanoparticles.
9. The LED display of claim 7 , further comprising source and drain contacts formed without forming junctions.
10. A non-volatile memory cell comprising:
a top gate;
a blocking oxide layer;
a charge trapping layer adjacent to at least a portion of the block oxide layer;
an Indium gallium zinc oxide (IGZO) layer adjacent to at least a portion of the charge trapping layer;
a gate oxide layer adjacent to at least a portion of the IGZO layer; and
a bottom gate.
11. The non-volatile memory cell of claim 10 , wherein the charge trapping layer comprises semiconducting nanoparticles.
12. The non-volatile memory cell of claim 10 , further comprising source and drain contacts formed without forming junctions.
13. The non-volatile memory cell of claim 10 , wherein during a WRITE operation the bottom gate is biased to enable an accumulation of electrons to form a channel in the IGZO layer between source and drain contacts, and wherein electrons are trapped by charge trapping layer.
14. The non-volatile memory cell of claim 10 , wherein the electrons are trapped by the charge trapping layer, wherein the trapped electrons shifts a threshold voltage of the bottom-gate.
15. The non-volatile memory cell of claim 10 , wherein a bias on the top gate accelerates programming of the non-volatile memory cell.
16. The non-volatile memory cell of claim 10 , wherein during an ERASE operation the bottom gate is biased to enable a depletion of electrons in the IGZO layer.
17. The non-volatile memory cell of claim 16 , wherein a bias on the top gate accelerates the depletion of the electrons.
18. The non-volatile memory cell of claim 13 , wherein during a READ operation current from the drain contact is sensed.
19. A mobile computing device comprising:
a processor;
a memory device; and
a Light Emitting Diode (LED) display having a plurality of pixel circuits, each including:
an LED; and
a non-volatile memory cell to adjust current to the LED, wherein the current to the LED is adjusted by applying data voltages to change a threshold voltage of the non-volatile memory cell.
20. The mobile computing device of claim 19 , wherein the pixel circuits each further comprise:
a first thin film transistor (TFT) coupled to the gate of the non-volatile memory cell to apply the data voltages; and
a second TFT coupled to the LED and the non-volatile memory cell.
21. The mobile computing device of claim 20 , wherein the first TFT is de-activated and the second TFT is activated during a Reset pulse performed at the non-volatile memory cell.
22. The mobile computing device of claim 21 , wherein the first TFT is activated and the second TFT is activated during a Write operation performed at the non-volatile memory cell.
23. The mobile computing device of claim 22 , wherein the first TFT is de-activated and the second TFT is de-activated during an Emission operation performed at the non-volatile memory cell.