Scan paths with gating, enable, and select decode control circuits
An integrated circuit includes combinational logic with flip-flops, parallel scan paths with a scan input for receiving test stimulus data to be applied to the combinational logic, combinational connections with the combinational logic for applying stimulus data to the combinational logic and receiving response data from the combinational logic, a scan output for transmitting test response data obtained from the combinational logic, and control inputs having an enable input and a select input for operating the parallel scan paths, each scan path includes flip-flops of the combinational logic that, in a test mode, are connected in series, compare circuitry indicates the result of a comparison of the received test response data and the expected data at a fail flag output, and one of the scan paths includes a scan cell having an input coupled to the fail flag output.
1. A semiconductor integrated circuit comprising:
(a) functional logic formed on a substrate, the functional logic including functional flip-flops;
(b) a test input bus of leads including a stimulus data input lead, a control input lead, a select input lead, and an enable input lead;
(c) scan paths, each scan path including functional flip-flops of the functional logic that, in a test mode, are connected in series, each scan path including a stimulus data input coupled to the stimulus data input lead, stimulus connections with the functional logic, response connections with the functional logic, a response data output, and a control input;
(d) gating circuitry having a first input connected to the control input lead, second inputs, and an output for each second input, each output being connected to the control input of a scan path; and
(e) select decode circuitry having an input connected to the control input lead, an input connected to the select lead, an input connected to the enable lead, and having scan path control outputs, each scan path control output being connected to one of the second inputs of the gating circuitry, and the select decode circuitry, in response to receiving an enable signal, decoding select codes from the select lead into gating circuitry control output signals.
2. The integrated circuit of claim 1 , including comparator circuitry having an expected data input, a mask data input, an input coupled to the response data output lead of each scan path, and a fail flag output.
3. The integrated circuit of claim 1 , in which the functional logic is combinational logic.