Executing a composite VLIW instruction having a scalar atom that indicates an iteration of execution
A processor core includes a storage device which stores a composite very large instruction word (VLIW) instruction, an instruction unit which obtains the composite VLIW instruction from the storage device and decodes the composite VLIW instruction to determine an operation to perform, and a composite VLIW instruction execution unit which executes the decoded composite VLIW instruction to perform the operation.
1. A processor core comprising:
a storage device which stores a composite very large instruction word (VLIW) instruction including a scalar atom;
an instruction unit which obtains the composite VLIW instruction from the storage device and decodes the composite VLIW instruction to determine an operation to perform; and
a composite VLIW instruction execution unit which executes the composite VLIW instruction to perform the operation, the composite VLIW instruction execution unit including a default setting which sets an iteration at which the scalar atom of the composite VLIW instruction is to be executed,
wherein the scalar atom indicates an iteration at which the scalar atom is to be executed instead of the iteration set by the default setting.
2. The processor core of claim 1 , wherein the composite VLIW instruction further comprises a vector atom and a control atom.
3. The processor core of claim 1 , wherein the composite VLIW instruction execution unit comprises a detector circuit which determines whether a REPEAT (REP) field in the composite VLIW instruction is REP=1 or REP>1, and
wherein if the detector circuit determines that the REPEAT field in the composite VLIW instruction is REP=1, then the composite VLIW instruction execution unit executes each atom in the composite VLIW instruction at a single iteration.
4. The processor core of claim 3 , wherein the composite VLIW instruction execution unit further comprises a composite VLIW instruction execution subunit, and if the detector circuit determines that the REPEAT field in the composite VLIW instruction is REP>1, then the composite VLIW instruction execution subunit executes the scalar atom of the composite VLIW instruction at a single iteration.
5. The processor core of claim 4 , wherein if the detector circuit determines that the REPEAT field in the composite VLIW instruction is REP>1, then the composite VLIW instruction execution subunit executes vector atoms of the composite VLIW instruction during all REP iterations.
6. The processor core of claim 5 , wherein if the detector circuit determines that the REPEAT field in the composite VLIW instruction is REP>1, then the composite VLIW instruction execution subunit executes branch and control atoms of the composite VLIW instruction at a single iteration.
7. The processor core of claim 6 , wherein the single iteration at which the composite VLIW instruction execution subunit executes branch and control atoms of the composite VLIW instruction comprises a last iteration.
8. The processor core of claim 6 , wherein the branch and control atoms of the composite VLIW instruction comprise a field indicating the iteration at which the composite VLIW instruction execution subunit executes the branch and control atoms.
9. The processor core of claim 6 , wherein the composite VLIW instruction execution unit comprises an iteration setting circuit which, based on a user input:
adjusts a default setting of an iteration at which to execute the branch and control atoms of the composite VLIW instruction; and
adjusts the default setting of an iteration which sets an iteration at which the scalar atom of the composite VLIW instruction is to be executed.
10. The processor core of claim 4 , wherein the single iteration at which the composite VLIW instruction execution subunit executes the scalar atom of the composite VLIW instruction comprises a first iteration.
11. The processor core of claim 4 , wherein the scalar atom of the composite VLIW instruction comprises a field indicating the iteration at which the composite VLIW instruction execution subunit executes the scalar atom.
12. The processor core of claim 1 , wherein the scalar atom includes a field indicating the iteration at which the scalar atom is to be executed, and the composite VLIW instruction execution unit executes the scalar atom at the iteration indicated by the field instead of the iteration indicated by the default setting.
13. A processor comprising the processor core of claim 1 .
14. A method of executing a composite very large instruction word (VLIW) instruction, the method comprising:
storing the composite VLIW instruction including a scalar atom;
obtaining the composite VLIW instruction, and decoding the composite VLIW instruction to determine an operation to perform; and
using a composite VLIW instruction execution unit, executing the composite VLIW instruction to perform the operation, the composite VLIW instruction execution unit including a default setting which sets an iteration at which the scalar atom of the composite VLIW instruction is to be executed,
wherein the scalar atom indicates an iteration at which the scalar atom is to be executed instead of the iteration set by the default setting.
15. The method of claim 14 , further comprising:
determining whether a REPEAT (REP) field in the composite VLIW instruction is REP=1 or REP>1; and
if the REPEAT field in the composite VLIW instruction is determined to be REP=1, then executing each atom in the composite VLIW instruction at a single iteration.
16. The method of claim 15 , further comprising:
if the REPEAT field in the composite VLIW instruction is determined to be REP>1, then executing the scalar atom of the composite VLIW instruction at a single iteration.
17. The method of claim 16 , further comprising:
if the REPEAT field in the composite VLIW instruction is determined to be REP>1, then executing vector atoms of the composite VLIW instruction during all REP iterations.
18. The method of claim 17 , further comprising:
if the REPEAT field in the composite VLIW instruction is determined to be REP>1, then executing branch and control atoms of the composite VLIW instruction at a single iteration.
19. A programmable storage medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus to perform the method of executing a composite very large instruction word (VLIW) instruction of claim 14 .
20. A method of generating a composite VLIW instruction, comprising:
inserting a scalar atom in the composite VLIW instruction to be executed at a single iteration, the scalar atom including a field indicating an iteration in which the scalar atom is to be executed;
inserting a vector atom in the composite VLIW instruction to be executed during all iterations indicated in a REPEAT field in the composite VLIW instruction; and
inserting branch and control atoms in the composite VLIW instruction to be executed at a single iteration,
wherein the scalar atom indicates an iteration at which the scalar atom is to be executed instead of an iteration set by a default setting of an execution unit.
21. The method of claim 20 , further comprising:
inserting in the branch and control atoms a field indicating an iteration in which the branch and control atoms are to be executed.