IP Library Granted Patent US 9,530,812
Granted Patent B2
US 9,530,812 · App. 15/087,695 · Granted Dec 27, 2016

Semiconductor device and method of manufacturing the same, and electronic apparatus

Inventors: Taku Umebayashi (Kanagawa, JP); Hiroshi Takahashi (Kanagawa, JP); Reijiroh Shohji (Tokyo, JP)
Assignee: Sony Corporation
H01L27/14634H01L27/1464H01L27/1469H01L27/14612H01L27/14621H01L27/14627H01L27/14632H01L27/14636H01L27/14643H01L27/14645H01L27/14687H04N5/225H04N5/374H01L2224/11
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Quick Facts
Patent No.
US 9,530,812
App. No.
15/087,695
Granted
Dec 27, 2016
Kind
B2
Abstract

A semiconductor device is provided as a back-illuminated solid-state imaging device. The device is manufactured by bonding a first semiconductor wafer with a pixel array in a half-finished product state and a second semiconductor wafer with a logic circuit in a half-finished product state together, making the first semiconductor wafer into a thin film, electrically connecting the pixel array and the logic circuit, making the pixel array and the logic circuit into a finished product state, and dividing the first semiconductor wafer and the second semiconductor being bonded together into microchips.

Claims (54)

1. An electronic apparatus, comprising:

an imaging device including:

a first semiconductor substrate having a light-incident side and including a pixel section, the pixel section including a photodiode and at least one of a transfer transistor, a reset transistor, or an amplification transistor,

a second semiconductor substrate having at least a part of a signal processing circuit, wherein the first semiconductor substrate and the second semiconductor substrate are bonded to each other,

a first multi-wiring layer formed at a side opposite to the light-incident side of the first semiconductor substrate, wherein the first multi-wiring layer is electrically connected to the pixel section,

a second multi-wiring layer formed at a first side of the second semiconductor substrate, wherein the side opposite to the light-incident side of the first semiconductor substrate and the first side of the second semiconductor substrate face each other, and wherein the signal processing circuit includes at least a plurality of wires of the second multi-wiring layer and a plurality of transistors,

a through-connection conductor extending from the light-incident side of the first semiconductor substrate to the second multi-wiring layer through the first semiconductor substrate in a peripheral section other than the pixel section, and

a first insulating layer disposed above the through-connection conductor,

wherein,

the through-connection conductor extends to the second multi-wiring layer by penetrating the first semiconductor substrate, and

the through-connection conductor has a first connection point connected to a wiring in the first multi-wiring layer and a second connection point connected to a wiring in the second multi-wiring layer; and

a lens configured to direct light to the light-incident side of the first semiconductor substrate.

2. The electronic apparatus according to claim 1 , wherein the first insulating layer includes at least one of SiCN, silicon nitride, or SiC.

3. The electronic apparatus according to claim 1 , further comprising:

a connection through-hole in which the through-connection conductor is disposed.

4. The electronic apparatus according to claim 3 , further comprising:

a second insulating layer disposed on at least a part of an inner wall of the connection through-hole.

5. The electronic apparatus according to claim 1 , wherein the first semiconductor substrate and the second semiconductor substrate are bonded to each other so that the first multi-wiring layer and the second multi-wiring layer face each other.

6. The electronic apparatus according to claim 1 , wherein a thickness of the first semiconductor substrate is less than a thickness of the second semiconductor substrate.

7. The electronic apparatus according to claim 1 , wherein the first semiconductor substrate and the second semiconductor substrate are bonded by using plasma bonding.

8. The electronic apparatus according to claim 1 , wherein at least one of a plasma TEOS film, a plasma SiN film, a SiON film, or a SiC film is formed on a bonding surface of the first semiconductor substrate or the second semiconductor substrate.

9. The electronic apparatus according to claim 1 , further including a color filter formed at the light-incident side of the first semiconductor substrate.

10. The electronic apparatus according to claim 1 , further including a micro-lens formed at the light-incident side of the first semiconductor substrate, wherein the through-connection conductor is formed in a predetermined area not corresponding to the micro-lens on the light-incident side of the first semiconductor substrate.

11. A semiconductor device comprising:

a first semiconductor substrate having a light-incident side and including a pixel section, the pixel section including a photodiode and at least one of a transfer transistor, a reset transistor, or an amplification transistor;

a second semiconductor substrate having at least a part of a signal processing circuit wherein the first semiconductor substrate and the second semiconductor substrate are bonded to each other

a first multi-wiring layer formed at a side opposite to the light-incident side of the first semiconductor substrate, wherein the first multi-wiring layer is connected to the pixel section;

a second multi-wiring layer formed at a first side of the second semiconductor substrate, wherein the side opposite to the light-incident side of the first semiconductor substrate and the first side of the second semiconductor substrate face each other, and wherein the signal processing circuit includes at least a plurality of wires of the second multi-wiring layer and a plurality of transistors; and

a through-connection conductor extending from the light-incident side of the first semiconductor substrate to the second multi-wiring layer through the first semiconductor substrate in a peripheral section other than the pixel section,

wherein,

the through-connection conductor extends to the second multi-wiring layer by penetrating the first semiconductor substrate, and

the through-connection conductor has a first connection point connected to a wiring in the first multi-wiring layer and a second connection point connected to a wiring in the second multi-wiring layer.

12. The semiconductor device according to claim 11 , further comprising:

a first insulating layer disposed above the through-connection conductor.

13. The semiconductor device according to claim 12 , wherein the first insulating layer includes at least one of SiCN, silicon nitride, or SiC.

14. The semiconductor device according to claim 11 , further comprising:

a connection through-hole in which the through-connection conductor is disposed.

15. The semiconductor device according to claim 14 , further comprising:

a second insulating layer disposed on at least a part of an inner wall of the connection through-hole.

16. The semiconductor device according to claim 11 , wherein the first multi-wiring layer is electrically connected to the pixel section via a connection conductor in the first multi-wiring layer.

17. The semiconductor device according to claim 11 , wherein the signal processing circuit is included in a logic circuit.

18. The semiconductor device according to claim 11 , wherein the first semiconductor substrate and the second semiconductor substrate are bonded to each other so that the first multi-wiring layer and the second multi-wiring layer face each other.

19. The semiconductor device according to claim 11 , wherein the through-connection conductor connects at least a lower wiring layer of the first multi-wiring layer and at least an upper wiring layer of the second multi-wiring layer.

20. The semiconductor device according to claim 19 , wherein the lower wiring layer of the first multi-wiring layer is connected to other wiring layers in the first multi-wiring layer.

21. The semiconductor device according to claim 11 , wherein the through-connection conductor connects a lowest wiring layer of the first multi-wiring layer and an uppermost wiring layer of the second multi-wiring layer.

22. The semiconductor device according to claim 11 , wherein a thickness of the first semiconductor substrate is less than a thickness of the second semiconductor substrate.

23. The semiconductor device according to claim 11 , wherein the first semiconductor substrate and the second semiconductor substrate are bonded by using a plasma bonding.

24. The semiconductor device according to claim 11 , wherein at least one of a plasma TEOS film, a plasma SiN film, a SiON film, or a SiC film is formed on a bonding surface of the first semiconductor substrate or the second semiconductor substrate.

25. The semiconductor device according to claim 11 , further including a color filter formed at the light-incident side of the first semiconductor substrate.

26. The semiconductor device according to claim 11 , further including a micro-lens formed at the light-incident side of the first semiconductor substrate, wherein the through-connection conductor is formed in a predetermined area not corresponding to the micro-lens on the light-incident side of the first semiconductor substrate.

27. The semiconductor device according to claim 11 , wherein a depth of the through-connection conductor is 5 μm to about 15 μm.

28. The semiconductor device according to claim 11 , wherein a diameter of the through-connection conductor at a contact area of the first connection point is 1 μm to 5 μm.

29. The semiconductor device according to claim 11 , wherein a diameter of the through-connection conductor at a contact area of the second connection point is 1 μm to 5 μm.

30. The semiconductor device according to claim 17 , wherein the through-connection conductor connects the pixel section and the logic circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2020
From: UMEBAYASHI, TAKU; TAKAHASHI, HIROSHI; SHOHJI, REIJIROH
To: SONY CORPORATION
Reel/Frame 053063/0514 →
Priority Claims (2)
JP 2009-068582 · Mar 19, 2009 · national
JP 2010-012586 · Jan 22, 2010 · national
Continuity (3)
Continuation 14834010 · Aug 24, 2015
Continuation 12722069 · Mar 11, 2010
Related Publication 20160218134A1 · Jul 28, 2016