Layout pattern for SRAM and manufacturing methods thereof
View Patent ↗A layout pattern of a static random access memory, including a first inverter and a second inverter constituting a latch circuit. A first inner access transistor, a second inner access transistor, a first outer access transistor and a second outer access transistor are electrically connected to the latch circuit, wherein the first outer access transistor has a first gate length, the first inner access transistor has a second gate length, and the first gate length is different from the second gate length.
1. A static random access memory (SRAM), comprising:
a substrate, a SRAM pattern disposed on the substrate, wherein the SRAM pattern comprising:
a first inverter and a second inverter constituting a latch circuit, wherein the first inverter includes a first pull-up transistor (PL 1 ) and a first pull-down transistor (PD 1 ), and the second inverter includes a second pull-up transistor (PL 2 ) and a second pull-down transistor (PD 2 );
a first inner access transistor (PG 2 A) and a second inner access transistor (PG 2 B) electrically connected to the latch circuit, wherein the first inner access transistor is electrically connected to a first word line and a second bit line, and the second inner access transistor is electrically connected to a second word line and a fourth bit line; and
a first outer access transistor (PG 1 A) and a second outer access transistor (PG 1 B) electrically connected to the latch circuit, wherein the first outer access transistor is electrically connected to the first word line and a first bit line, and the second outer access transistor is electrically connected to the second word line and a third bit line, in addition, the first outer access transistor (PG 1 A) has a first gate length, the first inner access transistor (PG 2 A) has a second gate length, and the first gate length is different from the second gate length.
2. The SRAM of claim 1 , further comprising performing an optical proximity correction (OPC) process to make the first gate length different from the second gate length.
3. The SRAM of claim 1 , wherein a ratio of the second gate length and the first gate length is between 0.58 and 0.99.
4. The SRAM of claim 3 , wherein a distance of the second gate length is from 14 nanometers to 24 nanometers.
5. The SRAM of claim 1 , wherein a gate of the first inner access transistor (PG 2 A) directly contacts a gate of the first outer access transistor (PG 1 A).
6. The SRAM of claim 1 , wherein a gate of the first inner access transistor (PG 2 A) and a gate of the first outer access transistor (PG 1 A) are arranged along a same symmetry axis.
7. The SRAM of claim 1 , wherein a gate of the second inner access transistor (PG 2 B) and a gate of the second outer access transistor (PG 1 B) are arranged along a same symmetry axis.
8. The SRAM of claim 1 , wherein the second outer access transistor has a third gate length, the second inner access transistor has a fourth gate length, and the third gate length is different from the fourth gate length.
9. The SRAM of claim 1 , further comprising performing a second optical proximity correction (OPC) process to make the third gate length different from the fourth gate length.
10. The SRAM of claim 1 , further comprising a plurality of fin structures disposed on the substrate.