IP Library Granted Patent US 10,217,738
Granted Patent B2
US 10,217,738 · App. 15/088,135 · Granted Feb 26, 2019

IGBT semiconductor device

Inventor: Tatsuya Naito (Matsumoto, JP)
Assignee: SMK Corporation
H01L27/0664H01L27/0727H01L29/0696H01L29/0834H01L29/1095H01L29/407H01L29/4238H01L29/42368H01L29/42376H01L29/7397
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Quick Facts
Patent No.
US 10,217,738
App. No.
15/088,135
Granted
Feb 26, 2019
Kind
B2
Abstract

A semiconductor device includes a semiconductor substrate, a base region formed in the semiconductor substrate on a front surface side thereof, a gate trench extending from a front surface side of the base region and penetrating thorough the base region, and a dummy trench extending from the front surface side of the base region and penetrating thorough the base region, where a portion of the dummy trench that extends beyond a back surface of the base region is longer than a portion of the gate trench that extends beyond the back surface of the base region.

Claims (83)

1. A semiconductor device comprising:

a semiconductor substrate;

a base region formed in the semiconductor substrate on a front surface side thereof;

a singular gate trench extending from a front surface side of the base region and penetrating through the base region;

a singular dummy trench extending from the front surface side of the base region and penetrating through the base region, a portion of the singular dummy trench that extends beyond a back surface of the base region being longer than a portion of the singular gate trench that extends beyond the back surface of the base region; and

an emitter electrode provided in the base region on a front surface side thereof, wherein

on the front surface side of the semiconductor substrate, an opening width of the singular gate trench is smaller than an opening width of the singular dummy trench, and

the singular dummy trench is connected to the emitter electrode.

2. The semiconductor device as set forth in claim 1 , wherein

a portion of the base region through which the singular gate trench is formed has the same thickness as a portion of the base region through which the singular dummy trench is formed.

3. The semiconductor device as set forth in claim 1 , further comprising

an accumulation region formed on a back surface of the base region, the accumulation region having a different conductivity type than the base region.

4. The semiconductor device as set forth in claim 3 wherein

the accumulation region is positioned closer to the base region than a bottom of the singular dummy trench is.

5. The semiconductor device as set forth in claim 4 , wherein

the accumulation region is positioned closer to a back surface of the semiconductor device than a bottom of the singular gate trench is and spaced away from the singular gate trench.

6. The semiconductor device as set forth in claim 5 , further comprising

a low-concentration region formed between the accumulation region and the bottom of the singular gate trench, the low-concentration region having the same conductivity type as the accumulation region and a lower impurity concentration than the accumulation region.

7. The semiconductor device as set forth in claim 1 , wherein

the singular gate trench includes:

a groove formed in the semiconductor substrate on the front surface side thereof;

an insulating film formed on an inner wall of the groove; and

an electrically conductive portion formed inside the insulating film within the groove, wherein

the insulating film formed at a bottom of the groove is thicker than the insulating film formed at an opening of the groove at the front surface of the semiconductor substrate.

8. The semiconductor device as set forth in claim 4 wherein

the singular gate trench includes:

a groove formed in the semiconductor substrate on the front surface side thereof;

an insulating film formed on an inner wall of the groove; and

an electrically conductive portion formed inside the insulating film within the groove, wherein

the insulating film positioned closer to a bottom of the groove than the accumulation region is is at least partially thicker than the insulating film positioned closer to an opening of the groove than the accumulation region is.

9. The semiconductor device as set forth in claim 1 , wherein

the singular dummy trench includes:

a front-side portion extending from the front surface of the semiconductor substrate; and

a bottom-side portion provided closer to a bottom of a groove than the front-side portion, the bottom-side portion having a larger width than the front-side portion.

10. The semiconductor device as set forth in claim 1 , wherein

the singular gate trench and the singular dummy trench each include:

a groove formed in the semiconductor substrate on the front surface side thereof;

an insulating film formed on an inner wall of the groove; and

an electrically conductive portion formed inside the insulating film within the groove, wherein

the insulating film formed at a bottom of the singular dummy trench is thicker than the insulating film in the singular gate trench.

11. A semiconductor device comprising:

a semiconductor substrate;

a base region formed in the semiconductor substrate on a front surface side thereof;

a singular gate trench extending from a front surface side of the base region and penetrating through the base region; and

a singular dummy trench extending from the front surface side of the base region and penetrating through the base region, a portion of the singular dummy trench that extends beyond a back surface of the base region being longer than a portion of the singular gate trench that extends beyond the back surface of the base region, wherein

on the front surface side of the semiconductor substrate, an opening width of the singular gate trench is smaller than an opening width of the singular dummy trench,

the semiconductor substrate includes:

a transistor portion having the base region, the singular gate trench and the singular dummy trench formed therein; and

a diode portion having the base region and an emitter trench formed therein, wherein

the emitter trench extends from the front surface side of the base region and penetrates through the base region.

12. The semiconductor device as set forth in claim 11 , wherein

the diode portion has a plurality of the emitter trenches that extend different lengths beyond the back surface of the base region.

13. The semiconductor device as set forth in claim 12 , wherein

at least one of the emitter trenches extends the same length beyond the back surface of the base region as the singular gate trench extends beyond the back surface of the base region, and

another at least one of the emitter trenches extends the same length beyond the back surface of the base region as the singular dummy trench extends beyond the back surface of the base region.

14. The semiconductor device as set forth in claim 11 , wherein

the diode portion has a plurality of the emitter trenches that extend the same length beyond the back surface of the base region.

15. The semiconductor device as set forth in claim 11 , wherein

a distance between adjacent ones of a plurality of the emitter trenches is the same as a distance between the singular gate trench and the singular dummy trench in the transistor portion.

16. A semiconductor device comprising:

a semiconductor substrate;

a base region formed in the semiconductor substrate on a front surface side thereof;

a singular gate trench extending from a front surface side of the base region and penetrating through the base region;

a singular dummy trench extending from the front surface side of the base region and penetrating through the base region, a portion of the singular dummy trench that extends beyond a back surface of the base region being longer than a portion of the singular gate trench that extends beyond the back surface of the base region; and

a well region formed in the semiconductor substrate on the front surface side thereof, the well region being positioned closer to an edge of the semiconductor substrate than the base region is, wherein

on the front surface side of the semiconductor substrate, an opening width of the singular gate trench is smaller than an opening width of the singular dummy trench, and

the singular dummy trench has a branch portion extending in a direction parallel to an edge of the well region at the front surface of the semiconductor substrate.

17. The semiconductor device as set forth in claim 16 , wherein

emitter regions of a first conductivity type and contact regions of a second conductivity type are alternately formed in the semiconductor substrate on the front surface side thereof, and

the branch portion is formed in one of the contact regions that is the closest to the well region.

18. The semiconductor device as set forth in claim 17 , comprising

a plurality of the singular dummy trenches separated from each other, wherein

the branch portions of the singular dummy trenches are aligned with each other on the same straight line.

19. The semiconductor device as set forth in claim 16 , further comprising

a back-surface trench formed in the semiconductor substrate on a back surface side thereof.

20. The semiconductor device as set forth in claim 19 , wherein

the back-surface trench is positioned closer to a center of the semiconductor substrate than the branch portion of the singular dummy trench is.

21. The semiconductor device as set forth in claim 19 , wherein

the back-surface trench is annularly formed at the back surface of the semiconductor substrate.

22. The semiconductor device as set forth in claim 1 , wherein

in a direction from the front surface side of the semiconductor substrate toward a back surface side of the semiconductor substrate, a distance from a bottom of an accumulation region formed on the back surface of the base region to a bottom of the singular dummy trench is longer than a distance from the bottom of the accumulation region to a bottom of the singular gate trench.

23. The semiconductor device as set forth in claim 1 , wherein

the base region contacting the singular dummy trench and the base region contacting the singular gate trench are located at the same depth.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 4, 2016
From: NAITO, TATSUYA
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 038178/0904 →
Priority Claims (2)
JP 2015-100323 · May 15, 2015 · national
JP 2015-223328 · Nov 13, 2015 · national
Continuity (1)
Related Publication 20160336404A1 · Nov 17, 2016