IP Library Granted Patent US 10,249,515
Granted Patent B2
US 10,249,515 · App. 15/089,136 · Granted Apr 2, 2019

Electronic device package

Inventors: Jimin Yao (Chandler, AZ); Eric Li (Chandler, AZ); Shawna Liff (Scottsdale, AZ)
Assignee: Intel Corporation
H01L21/563H01L21/565H01L23/3185H01L2021/60022
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Quick Facts
Patent No.
US 10,249,515
App. No.
15/089,136
Granted
Apr 2, 2019
Kind
B2
Abstract

Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate, an electronic component disposed on the substrate and electrically coupled to the substrate, and an underfill material disposed at least partially between the electronic component and the substrate. A lateral portion of the underfill material can comprises a lateral surface extending away from the substrate and a meniscus surface extending between the lateral surface and the electronic component.

Claims (15)

1. An electronic device package, comprising:

a substrate;

an electronic component disposed on the substrate and electrically coupled to the substrate; and

an underfill material disposed at least partially between the electronic component and the substrate, wherein a lateral portion of the underfill material comprises an exposed lateral surface extending away from the substrate and intersecting a meniscus surface extending between the lateral surface and the electronic component, wherein a height of the lateral surface from the substrate is greater than a length of the meniscus surface, and wherein the lateral surface comprises an irregular surface that has a concavity from an upper surface of the substrate.

2. The electronic device package of claim 1 , wherein an intersection of the meniscus surface and the lateral surface defines an edge.

3. The electronic device package of claim 1 , wherein a height of the lateral surface from the substrate is greater than a gap between the electronic component and the substrate.

4. The electronic device package of claim 1 , wherein the electronic component comprises a semiconductor device.

5. The electronic device package of claim 1 , wherein the electronic component is coupled to the substrate through a plurality of solder bumps.

6. An electronic device package, comprising:

a substrate;

an electronic component disposed on the substrate and electrically coupled to the substrate; and

an underfill material disposed at least partially between the electronic component and the substrate, wherein a lateral portion of the underfill material extends from a lateral side of the electronic component to the substrate, the lateral portion of the underfill material having an edge between two surfaces of the underfill material, wherein one of the two surfaces of the underfill material comprises an exposed lateral surface that extends from the substrate, and the other of the two surfaces of the underfill material comprises a meniscus surface, wherein a height of the lateral surface from the substrate is greater than a length of the meniscus surface, and wherein the lateral surface comprises an irregular surface that has a concavity from an upper surface of the substrate.

7. The electronic device package of claim 6 , wherein a height of the lateral surface from the substrate is greater than a gap between the electronic component and the substrate.

8. The electronic device package of claim 6 , wherein the electronic component comprises a semiconductor device.

9. The electronic device package of claim 6 , wherein the electronic component is coupled to the substrate through a plurality of solder bumps.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 2, 2016
From: YAO, JIMIN; LI, ERIC; LIFF, SHAWNA
To: INTEL CORPORATION
Reel/Frame 038178/0355 →
Continuity (1)
Related Publication 20170287735A1 · Oct 5, 2017