Semiconductor device and structure
A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection, where the first layer includes a first clock distribution structure, where the second layer includes a second clock distribution structure, where the device includes a Phase Lock Loop (“PLL”) circuit, where the second clock distribution structure is connected to the Phase Lock Loop (“PLL”) circuit, and where the second transistors are aligned to the first transistors with less than 200 nm alignment error.
1. A 3D device, comprising:
a first layer comprising first transistors, said first transistors interconnected by a first layer of interconnection;
a second layer comprising second transistors, said second transistors overlaying said first layer of interconnection,
wherein said first layer comprises a first clock distribution structure,
wherein said second layer comprises a second clock distribution structure,
wherein said device comprises a Phase Lock Loop (“PLL”) circuit,
wherein said second clock distribution structure is connected to said Phase Lock Loop (“PLL”) circuit, and
wherein said second transistors are aligned to said first transistors with less than 200 nm alignment error.
2. The 3D device according to claim 1 ,
wherein said second clock distribution structure is connected to said first clock distribution structure with a plurality of through layer vias, and
wherein at least one of said through layer vias has a diameter of less than 400 nm.
3. The 3D device according to claim 1 , further comprising:
a heat spreader layer disposed between said first layer and said second layer.
4. The 3D device according to claim 1 , further comprising:
a heat removal path between said second transistors and an external surface of said device.
5. The 3D device according to claim 1 , further comprising:
a power distribution network to provide power to said second transistors,
wherein said power distribution network provides a heat removal path from said second transistors to an external surface of said device.
6. The 3D device according to claim 1 ,
wherein said first layer comprises a plurality of first flip-flops connected to form a first scan chain, and
wherein said second layer comprises a plurality of second flip-flops connected to form a second scan chain.
7. The 3D device according to claim 1 ,
wherein said second clock distribution structure is connected to said first clock distribution structure.
8. A 3D device, comprising:
a first layer comprising first transistors, said first transistors interconnected by a first layer of interconnection;
a second layer comprising second transistors, said second transistors overlaying said first layer of interconnection,
wherein said first layer comprises a first clock distribution structure,
wherein said second layer comprises a second clock distribution structure,
wherein said device comprises a Phase Lock Loop (“PLL”) circuit,
wherein said second clock distribution structure is connected to said Phase Lock Loop (“PLL”) circuit, and
wherein said second layer thickness is less than 1 micrometer.
9. The 3D device according to claim 8 , further comprising:
a plurality of through layer vias as part of a plurality of connection paths between said first transistors and said second transistors,
wherein at least one of said through layer vias has a diameter of less than 400 nm.
10. The 3D device according to claim 8 , further comprising:
a heat spreader layer disposed between said first layer and said second layer.
11. The 3D device according to claim 8 , further comprising:
a heat removal path between said second transistors and an external surface of said device.
12. The 3D device according to claim 8 , further comprising:
a power distribution network to provide power to said second transistors,
wherein said power distribution network provides a heat removal path from said second transistors to an external surface of said device.
13. The 3D device according to claim 8 ,
wherein said second clock distribution structure is connected to said first clock distribution structure.
14. A 3D device, comprising:
a first layer comprising first transistors, said first transistors interconnected by a first layer of interconnection;
a second layer comprising second transistors, said second transistors overlaying said first layer of interconnection,
wherein said first layer comprises a first clock distribution structure,
wherein said second layer comprises a second clock distribution structure,
wherein said device comprises a Phase Lock Loop (“PLL”) circuit,
wherein said second clock distribution structure is connected to said Phase Lock Loop (“PLL”) circuit,
wherein said second clock distribution structure is connected to said first clock distribution structure with a plurality of through layer vias, and
wherein at least one of said through layer vias has a diameter of less than 400 nm.
15. The 3D device according to claim 14 ,
wherein said second layer thickness is less than 1 micrometer.
16. The 3D device according to claim 14 ,
wherein said Phase Lock Loop (“PLL”) circuit has a plurality of connections to an external component.
17. The 3D device according to claim 14 ,
wherein said second clock distribution structure is connected to said first clock distribution structure.
18. The 3D device according to claim 14 ,
wherein said first layer comprises a plurality of first flip-flops connected to form a first scan chain, and
wherein said second layer comprises a plurality of second flip-flops connected to form a second scan chain.
19. The 3D device according to claim 14 , further comprising:
a heat spreader layer disposed between said first layer and said second layer.
20. The 3D device according to claim 14 , further comprising:
a heat removal path between said second transistors and an external surface of said device.