Semiconductor package and manufacturing method thereof
Thermal resistance is reduced from an element surface of a semiconductor chip to the rear surface of a semiconductor package. Split patterning of a metal is easily carried out, stress produced by a thermal expansion coefficient between silicon and metal is significantly reduced and environment reliability is improved. Low cost is realized by manufacturing a semiconductor package without using a TIM material. A semiconductor package is provided including a semiconductor chip including a first surface and a second surface opposed to the first surface and covered with a resin, an electrode being arranged over the first surface, a first wiring connected to the first surface directly or via a first opening arranged in the resin, and a second wiring connected to the second surface via a second opening arranged in the resin.
1. A semiconductor package comprising:
a first semiconductor chip and a second semiconductor chip, each including a first surface having a first electrode and a second electrode, and a second surface over and opposed to the first surface, the first semiconductor chip and the second semiconductor chip being covered with a resin;
a first wiring over the resin, the first wiring connecting the first electrodes of the first semiconductor chip and the second semiconductor chip to each other via a first opening and a second opening arranged in the resin; and
a second wiring directly connecting the second surface of the first semiconductor chip to the second electrode of the second semiconductor chip via a third opening arranged in the resin.
2. The semiconductor package according to claim 1 , wherein the first wiring has a stacked structure of Au, Ni and Cu in this order.
3. The semiconductor package according to claim 1 , wherein the second wiring has a stacked structure of a barrier metal and Cu.
4. The semiconductor package according to claim 1 , further comprising a plurality of openings in the resin, the plurality of openings overlapping with the second surface of the first semiconductor chip.
5. The semiconductor package according to claim 1 ,
wherein the second wiring has a slit overlapping with the first semiconductor chip.
6. The semiconductor package according to claim 5 ,
wherein the slit has a circular shape, a L-shape, or an arc shape.
7. The semiconductor package according to claim 1 ,
wherein the third opening is located between the first semiconductor chip and the second semiconductor chip.
8. The semiconductor package according to claim 1 ,
wherein the first wiring overlaps with the first semiconductor chip.
9. The semiconductor package according to claim 1 ,
wherein the second semiconductor chip is arranged to be closer to the second opening than the first opening.
10. The semiconductor package according to claim 1 ,
wherein the first semiconductor chip is arranged so as to be sandwiched between the first opening and the second opening.