Method for doping source and drain regions of a transistor by means of selective amorphisation
Method including the steps consisting in: forming source and drain semiconductor blocks comprising a first layer based on a first crystalline semiconductor material surmounted by a second layer ( 16 ) based on a second crystalline semiconductor material different from the first semiconductor material, making amorphous and selectively doping the second layer ( 16 ) by means of one or more implantation(s), carrying out a recrystallisation of the second layer and an activation of dopants by means of at least one thermal annealing.
1. A method for producing a microelectronic device provided with at least one transistor formed on a semiconductor on insulator type substrate including the steps consisting in:
providing a structure including, on an insulating layer of a semiconductor on insulator substrate: a first semiconductor layer based on a first crystalline semiconductor material, the first semiconductor material being based on Si 1−x Ge x (with x≥0), the first layer comprising a given zone in which a channel of the transistor is able to be produced, semiconductor blocks being arranged on either side of said zone intended to form source and drain blocks, said structure further comprising a gate block and first insulating spacers laid out on either side of the gate block and lying on said given zone of the first layer, then
thinning the first layer on either side of said given zone,
formation of a second layer based on a second crystalline semiconductor material different from the first semiconductor material on the thinned regions of the first layer so as to complete the formation of said source and drain blocks, the second semiconductor material being based on Si 1−y Ge y with 0≤x<y, with y−x>0.1,
then
making amorphous and doping the second layer by means of one or more implantation(s), the first material, the second material, and the implantation(s) being provided so as to carry out a selective amorphisation of the second semiconductor material while conserving the crystalline structure of the first semiconductor material, an interface between the first layer and the second layer corresponding to an interface between a region made amorphous and a region of which the crystalline structure has been conserved,
carrying out a recrystallisation of the second layer as well as an activation of dopants by means of at least one thermal annealing.
2. The method according to claim 1 , further including after thinning of the first layer and prior to the formation of the second layer, a step consisting in:
removing a thickness of the regions of the first layer on either side of the spacers and a part of the given zone situated facing the spacers.
3. The method according to claim 1 , wherein the formation of the second layer includes at least one first growth by epitaxy of the second semiconductor material up to at least the level of an upper face of the given zone of the first layer on which lies the gate block.
4. The method according to claim 3 , wherein after the first growth by epitaxy an amorphisation of the second semiconductor material is carried out, said amorphisation being selective with respect to the first semiconductor material.
5. The method according to claim 3 , wherein after the first growth by epitaxy a second growth by epitaxy is carried out such as to form a third semiconductor layer on the second semiconductor layer.
6. The method according to claim 5 , wherein after the first growth by epitaxy and prior to the second growth by epitaxy second insulating spacers are formed against the first insulating spacers.
7. The method according to claim 5 , wherein during the second growth by epitaxy an in-situ doping of the third semiconductor layer is carried out.
8. The method according to claim 5 , wherein after the second growth by epitaxy an amorphisation of the material of the third semiconductor layer and the second semiconductor material is carried out, said amorphisation being selective in respect with the first semiconductor material.
9. The method according to claim 5 , wherein after the first growth by epitaxy and prior to the second growth by epitaxy, a doping of the second semiconductor material is carried out, the implantation(s) then being carried out after the second growth by epitaxy such as to make amorphous and to dope the third semiconductor layer and the second semiconductor layer.
10. The method according to claim 1 , wherein the transistor is of NMOS type, the first semiconductor material being based on Si whereas the second semiconductor material is based on Si 1−y Ge y , with 5%<y<15%.
11. The method according to claim 10 , wherein a third semiconductor layer is formed on the second semiconductor layer, the third layer being based on Si:C.
12. The method according to claim 1 , wherein the transistor is of PMOS type, the first semiconductor material being based on Si whereas the second semiconductor material is based on Si 1−y Ge y with y>20%,
or
the first material is based on Si 1−x Ge x with x<25% and the second material is Si 1−y Ge y with y>35%.
13. Method according to claim 12 , wherein a third semiconductor layer is formed on the second semiconductor layer, the third layer being based on Si 1−z Ge z with y≤z.