Storage bitcell with isolation
A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.
1. A circuit comprising:
a first inverter comprising a first internal node;
a second inverter comprising a second internal node and cross-coupled to the first inverter;
a first feedback transistor comprising a first terminal and a second terminal, the first terminal being connected to the first internal node;
a second feedback transistor comprising a first terminal and a second terminal, the first terminal being connected to the second internal node;
a first p-channel transistor comprising a drain terminal connected to the first inverter, and a gate connected to the second terminal of the second feedback transistor;
a second p-channel transistor comprising a drain terminal connected to the second inverter, and a gate connected to the second terminal of the first feedback transistor;
a first n-channel transistor comprising a drain terminal connected to the first inverter, and a gate connected to the second terminal of the second feedback transistor; and
a second n-channel transistor comprising a drain terminal connected to the second inverter, and a gate connected to the second terminal of the first feedback transistor.
2. The circuit as set forth in claim 1 , further comprising:
a first word-line connected to a gate of the first feedback transistor; and
a second word-line connected to a gate of the second feedback transistor.
3. The circuit as set forth in claim 2 , further comprising:
a first access transistor comprising a first terminal, a second terminal and a gate, the first terminal being connected to the second terminal of the first feedback transistor, the gate being connected to the first word-line;
a first bit-line connected to the second terminal of the first access transistor;
a second access transistor comprising a first terminal, a second terminal and a gate, the first terminal being connected to the second terminal of the second feedback transistor, the gate being connected to the second word-line; and
a second bit-line connected to the second terminal of the second access transistor.
4. The circuit as set forth in claim 3 , further comprising:
a transistor comprising a first terminal, a second terminal and a gate connected to the second terminal of the second feedback transistor;
a read-line-to-ground connected to the first terminal of the transistor; and
a read line connected to the second terminal of the transistor.
5. The circuit as set forth in claim 4 , further comprising:
a voltage supply rail, the first and second p-channel transistors each comprising a source terminal connected to the voltage supply rail; and
a ground, the first and second n-channel transistors each comprising a source terminal connected to the ground.
6. The circuit as set forth in claim 4 , wherein
the first and second feedback transistors are each p-channel transistors; and
the first and second access transistors are each n-channel transistors.