IP Library › Granted Patent US 10,007,631
Granted Patent B2
US 10,007,631 · App. 15/093,489 · Granted Jun 26, 2018

Display device

Inventors: Min Young Park (Yongin-si, KR); Ki Hyun Pyun (Yongin-si, KR)
Assignee: Samsung Display Co., Ltd.
G06F13/4022G06F12/0246G06F13/4282G06F2212/7206
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Quick Facts
Patent No.
US 10,007,631
App. No.
15/093,489
Granted
Jun 26, 2018
Kind
B2
Abstract

There is provided a display device including an input unit configured to connect an external device to a serial peripheral interface (SPI) through a plurality of connection lines, a switching unit configured to connect the input unit and a flash memory of a driving board to the SPI, a data register configured to output connection setting data for determining a connection state of the switching unit, and a timing controller configured to output a control signal for determining the connection setting data according to an input of a write enable line among the plurality of connection lines.

Claims (26)

1. A display device comprising:

an input unit configured to connect an external device to a serial peripheral interface (SPI) through a plurality of connection lines;

a switching unit configured to connect the input unit and a flash memory of a driving board to the SPI;

a data register configured to output connection setting data for determining a connection state of the switching unit; and

a timing controller configured to output a control signal for determining the connection setting data according to an input of a write enable (write EN) line among the plurality of connection lines,

wherein the flash memory is configured to store unevenness correction data of each of a plurality of pixels of the display device.

2. The display device of claim 1 , further comprising a converter configured to generate connection setting data through an inter-integrated circuit (I2C) interface by receiving the control signal from the timing controller.

3. The display device of claim 1 , wherein the switching unit comprises:

a first switch circuit configured to selectively connect the timing controller and the flash memory to each other; and

a second switch circuit configured to selectively connect the flash memory and the input unit to each other.

4. The display device of claim 3 , wherein, when the input of the write EN line is at a logic high, the first switch circuit is activated, and the second switch circuit is deactivated.

5. The display device of claim 3 , wherein, when the input of the write EN line is at a logic low, the second switch circuit is activated, and the first switch circuit is deactivated.

6. The display device of claim 3 , wherein, when the input of the write EN line is at a logic high, the connection setting data comprises data for connecting the first switch circuit.

7. The display device of claim 3 , wherein, when the input of the write EN line is at a logic low, the connection setting data comprises data for connecting the second switch circuit.

8. A method for connecting a control circuit and source circuit of a display device to each other, the method comprising:

connecting, by an input unit, an external device to a serial peripheral interface (SPI) through a plurality of connection lines;

connecting, by a switching unit, the input unit and a flash memory of a driving board to the SPI;

outputting, by a data register, connection setting data for determining a connection state of the switching unit; and

outputting, by a timing controller, a control signal for determining the connection setting data according to an input of a write enable (write EN) line among the plurality of connection lines,

wherein the flash memory is configured to store unevenness correction data of each of a plurality of pixels of the display device.

9. A system for connecting a control circuit and source circuit of a display device to each other, the system comprising means for:

connecting an external device to a serial peripheral interface (SPI) through a plurality of connection lines;

connecting an input unit and a flash memory of a driving board to the SPI through a switching unit;

outputting connection setting data for determining a connection state of the switching unit; and

outputting a control signal for determining the connection setting data according to an input of a write enable (write EN) line among the plurality of connection lines,

wherein the flash memory is configured to store unevenness correction data of each of a plurality of pixels of the display device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2016
From: PARK, MIN YOUNG; PYUN, KI HYUN
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 038229/0031 →
Priority Claims (1)
KR 10-2015-0059910 · Apr 28, 2015 · national
Continuity (1)
Related Publication 20160321208A1 · Nov 3, 2016
Cited By (1)
US 12,475,832