Semiconductor devices having dummy gate structure for controlling channel stress

1. A semiconductor device, comprising:

a gate structure on a substrate, the gate structure including a first gate insulation pattern, a conductive pattern for controlling a threshold voltage, a first gate electrode and a first mask sequentially stacked;

a dummy gate structure spaced apart from the gate structure, the dummy gate structure including a first stressor pattern including titanium oxide; and

source/drain regions adjacent to the gate structure, the source/drain regions doped with p-type impurities.

2. The semiconductor device of claim 1 , wherein the dummy gate structure has a stacked structure different from a stacked structure of the gate structure.

3. The semiconductor device of claim 1 , wherein the dummy gate structure includes a second gate insulation pattern, the first stressor pattern, a second gate electrode and a second mask sequentially stacked.

4. The semiconductor device of claim 1 , wherein the conductive pattern of the gate structure includes titanium.

5. The semiconductor device of claim 1 , wherein the first stressor pattern of the dummy gate structure includes an oxide of a material included in the conductive pattern.

6. The semiconductor device of claim 1 , further comprising a barrier pattern including titanium on the conductive pattern of the gate structure.

7. The semiconductor device of claim 6 , further comprising a second stressor pattern on the first stressor pattern of the dummy gate structure, wherein the second stressor pattern includes an oxide of a material included in the barrier pattern.

8. The semiconductor device of claim 1 , wherein a width of the dummy gate structure is substantially equal to or greater than a width of the gate structure.

9. The semiconductor device of claim 1 , further comprising a plurality of dummy gate structures adjacent to each of opposite sidewalls of the gate structure.

10. The semiconductor device of claim 1 , further comprising an active fin protruding from a surface of the substrate, wherein each of the gate structure and the dummy gate structure is formed on sidewalls and a top surface of the active fin, and extends in a direction crossing the active fin.

11. The semiconductor device of claim 1 , further comprising an additional dummy gate structure between the gate structure and the dummy gate structure, wherein the additional dummy gate structure has a stacked structure substantially the same as a stacked structure of the gate structure.

12. A semiconductor device, comprising:

A first transistor including:

a first gate structure on a substrate, the first gate structure including a first gate insulation pattern, a first conductive pattern for controlling a threshold voltage, a first gate electrode and a first mask sequentially stacked;

a first dummy gate structure spaced apart from the first gate structure, the first dummy gate structure including a first stressor pattern including titanium oxide; and

first source/drain regions adjacent to the first gate structure, the first source/drain regions doped with p-type impurities; and

a second transistor including;

a second gate structure on the substrate, the second gate structure including a second gate insulation pattern, a second conductive pattern for controlling a threshold voltage, a second gate electrode and a second mask sequentially stacked;

a second dummy gate structure spaced apart from the second gate structure, the second dummy gate structure not including titanium and titanium oxide; and

second source/drain regions adjacent to the second gate structure, the second source/drain regions doped with n-type impurities.

13. The semiconductor device of claim 12 , wherein the second dummy gate structure includes the second gate insulation pattern, the second gate electrode and the second mask sequentially stacked.

14. The semiconductor device of claim 12 , wherein the first conductive pattern has a work function more than about 4.5 eV, and the second conductive pattern has a work function less than about 4.5 eV.

15. The semiconductor device of claim 12 , wherein the first and the second conductive patterns include titanium.

16. The semiconductor device of claim 12 , wherein a width of the first dummy gate structure is substantially equal to or greater than a width of the first gate structure.

17. The semiconductor device of claim 12 , further comprising a first active fin protruding from a surface of the substrate, wherein each of the first gate structure and the first dummy gate structure is formed on sidewalls and a top surface of the first active fin, and extends in a direction crossing the first active fin.

18. The semiconductor device of claim 12 , further comprising a second active fin protruding from a surface of the substrate, wherein each of the second gate structure and the second dummy gate structure is formed on sidewalls and a top surface of the second active fin, and extends in a direction crossing the second active fin.

19. The semiconductor device of claim 12 , further comprising an additional first dummy gate structure between the first gate structure and the first dummy gate structure, wherein the additional first dummy gate structure has a stacked structure substantially the same as a stacked structure of the first gate structure.

20. A semiconductor device, comprising:

a gate structure on a substrate, the gate structure including a first gate insulation pattern, a conductive pattern for controlling a threshold voltage, a first gate electrode and a first mask sequentially stacked, the conductive pattern including titanium;

a dummy gate structure spaced apart from the gate structure, the dummy gate structure not including titanium and titanium oxide; and

source/drain regions adjacent to the gate structure, the source/drain regions doped with n-type impurities,

wherein the dummy gate structure has a stacked structure different from a stacked structure of the gate structure.