Methods and systems for reducing crosstalk using sequential non-linear vectoring

1. A method comprising:

determining a first set of first lines and a second set of second lines in a system;

obtaining input signals to be transmitted over the first set of first lines and the second set of second lines, the second set of second lines including at least two lines;

obtaining a channel;

determining a vectoring matrix based on the channel;

processing, within the first set, the input signals for the first lines in parallel based on the vectoring matrix, the processing within the first set including a first linear matrix operation and a first non-linear operation;

processing, within the second set, the input signals for the second lines in parallel based on the vectoring matrix, the processing within the second set including a second linear matrix operation and a second non-linear operation; and

processing the first set and the second set sequentially based on the vectoring matrix, the processing the second set being based on at least a portion of the processing the input signals for the first lines.

2. A method comprising:

determining a first set of first lines and a second set of second lines in a system;

obtaining input signals to be transmitted over the first set of first lines and the second set of second lines, the second set of second lines including at least two lines;

determining a vectoring matrix;

processing, within the first set, the input signals for the first lines in parallel based on the vectoring matrix;

processing, within the second set, the input signals for the second lines in parallel based on the vectoring matrix; and

processing the first set and the second set sequentially based on the vectoring matrix, the processing the second set being based on at least a portion of the processing the input signals for the first lines, wherein the determining the vectoring matrix includes,

determining a lattice reduction matrix, the lattice reduction matrix including a first sub-matrix associated with the first set of first lines and a second sub-matrix associated with the second set of second lines; and

determining a lower-diagonal matrix, the lower-diagonal matrix including a third sub-matrix associated with the first set of first lines and the second set of second lines, the lattice reduction matrix and the lower-diagonal matrix forming at least a part of the vectoring matrix.

3. The method of claim 2 , wherein the processing within the first set includes,

generating scaled shifted signals for the first lines based on the input signals for the first lines, the first sub-matrix and a rounding operator.

4. The method of claim 3 , further comprising:

generating a first precoded vector based on the scaled shifted signals and a scaling matrix.

5. The method of claim 4 , wherein the generating the first precoded vector includes generating the first precoded vector by

x 1 =Q 11 A 11 ( u 1 +s 1 )+ Q 12 A 22 ( u 2 ′+s 2 )

where x 1 is the first precoded vector, Q is a block-orthogonal matrix and Q 11 and Q 12 are submatrices of the block-orthogonal matrix, A 11 is a fourth sub-matrix, the fourth sub-matrix being a sub-matrix of the scaling matrix, A 22 is a fifth sub-matrix, the fifth sub-matrix being a sub-matrix of the scaling matrix, u 1 is the input signals for the first lines, s 1 is shifted signals for the first lines, u 2 ′ is modified input signals for the second lines and s 2 is shifted signals for the second lines.

6. The method of claim 3 , wherein the processing the first set and the second set sequentially includes,

generating feeding signals by applying the scaled shifted signals for the first lines to at least the third sub-matrix; and

adding the feeding signals to scaled input signals of the input signals for the second lines to generate modified input signals for the second lines.

7. The method of claim 6 , wherein the processing within the second set includes,

generating scaled shifted signals for the second lines based on the modified input signals for the second lines, the second sub-matrix and a scaling matrix.

8. The method of claim 2 , wherein the processing within the first set includes,

generating scaled shifted signals for the first lines based on the input signals for the first lines, the first sub-matrix and a modulo operator.

9. The method of claim 8 , further comprising:

generating a first precoded vector based on the scaled shifted signals for the first lines and a block-orthogonal matrix.

10. The method of claim 8 , wherein the processing within the second set includes,

generating modified scaled input signals for the second lines based on the second sub-matrix of the lattice reduction matrix and the input signals for the second lines.

11. The method of claim 10 , wherein the processing the first set and the second set sequentially includes,

generating feeding signals by applying the scaled shifted signals for the first lines to the third sub-matrix; and

adding the feeding signals to scaled input signals for the second lines to generate the modified scaled input signals for the second lines.

12. The method of claim 11 , wherein the processing within the second set includes,

generating scaled shifted signals for the second lines based on the modified scaled input signals for the second lines and the modulo operator.

13. The method of claim 2 , wherein the lattice reduction matrix is a unimodular matrix other than an identity matrix.

14. A device comprising:

a memory storing computer readable instructions; and

a processor configured to execute the computer readable instructions to,

determine a first set of first lines and a second set of second lines in a system;

obtain input signals to be transmitted over the first set of first lines and the second set of second lines, the second set of second lines including at least two lines;

obtain a channel;

determine a vectoring matrix based on the channel;

process, within the first set, the input signals for the first lines in parallel based on the vectoring matrix, the processor configured to execute the computer readable instructions to perform a first linear matrix operation and a first non-linear operation to process the input signals for the first lines;

process, within the second set, the input signals for the second lines in parallel based on the vectoring matrix, the processor configured to execute the computer readable instructions to perform a second linear matrix operation and a second non-linear operation to process the input signals for the second lines; and

process the first set and the second set sequentially based on the vectoring matrix, the processing the second set being based on at least a portion of the processing the input signals for the first lines.