Power semiconductor device with a double metal contact and related method
A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.
1. A method of fabricating a power semiconductor device, said method comprising:
depositing a first metal layer over an active region formed in a semiconductor body, said active region including source regions and gate electrodes;
dry etching said first metal layer to obtain a first source metal layer and a metallic gate bus that is laterally spaced from said first source metal layer;
forming a buffer body over said gate bus;
depositing a second metal layer over said first metal layer and over said buffer body; and
patterning said second metal layer to obtain a first pad which contacts said first source metal layer and a second pad spaced from said first pad, said second pad being separated from said metallic gate bus by said buffer body, said second pad being electrically coupled to said metallic gate bus by an insulated via that extends through said buffer body.
2. The method of claim 1 , wherein said first metal layer and said gate bus are less than 2 microns thick.
3. The method of claim 1 , wherein said second metal layer is more than 4 microns thick.
4. The method of claim 1 , wherein said second metal layer is more than 4-20 microns thick.
5. The method of claim 1 , wherein said buffer body comprises polyimide.
6. The method of claim 1 , further comprising a hermetic sealant body disposed between said gate bus and said buffer body.
7. The method of claim 6 , wherein said hermetic sealant body comprises a stack of PSG and silicon nitride.
8. A method of fabricating a power semiconductor device, said method comprising:
depositing a first metal layer over an active region formed in a semiconductor body, said active region including source regions and gate electrodes;
dry etching said first metal layer to obtain a first source metal layer and a gate bus that is laterally spaced from said first source metal layer, said gate bus including a metallic gate bus over a polysilicon gate bus and an insulation body between said polysilicon gate bus and said semiconductor body, wherein said gate bus is not disposed within a trench;
forming a buffer body over said gate bus;
depositing a second metal layer over said first metal layer and over said buffer body; and
patterning said second metal layer to obtain a first pad which contacts said first source metal layer and a second pad spaced from said first pad, said second pad being separated from said gate bus by said buffer body, said second pad being electrically coupled to said gate bus by an insulated via that extends through said buffer body.
9. The method of claim 8 , wherein a gate pad is coupled to said metallic gate bus through said buffer body.
10. The method of claim 8 , wherein said first metal layer is less than 2 microns thick.
11. The method of claim 8 , wherein said metallic gate bus is less than 2 microns thick.
12. The method of claim 8 , wherein said second metal layer is more than 4 microns thick.
13. The method of claim 8 , wherein said second metal layer is more than 20 microns thick.
14. The method of claim 8 , wherein said buffer body comprises polyimide.
15. The method of claim 8 , further comprising a hermetic sealant body between said gate bus and said buffer body.
16. The method of claim 15 , wherein said hermetic sealant body comprises a stack of PSG and silicon nitride.
17. A method of fabricating a power semiconductor device, said method comprising:
depositing a first metal layer over an active region formed in a semiconductor body, said active region including source regions and gate electrodes;
dry etching said first metal layer to obtain a first source metal layer and a metallic gate bus that is laterally spaced from said first source metal layer;
forming a buffer body over said gate bus; and
depositing a second metal layer over said first metal layer and over said buffer body,
wherein a hermetic sealant body is disposed between said gate bus and said buffer body.
18. The method of claim 17 , wherein said hermetic sealant body comprises a stack of PSG and silicon nitride.