Consolidating write transactions for a network device

1. A network device comprising:

a network interface operable to send and receive a packet;

a bus interface operable to send and receive bus traffic on a bus; and

processing logic coupled to the bus interface and the network interface, wherein the processing logic is operable to:

store information associated with the packet in a queue;

mask interrupts for the network device;

send an interrupt to a host processor to notify the host processor of completion of packet processing;

receive, by the bus interface, a Memory-Mapped Input/Output (MMIO) write transaction that includes an update for a pointer associated with a completion queue and an interrupt unmasking value;

update the pointer associated with the completion queue; and unmask the interrupts for the network device based on the MMIO write transaction.

2. The network device of claim 1 , wherein storing the information associated with the packet includes:

writing the packet to a memory location in a packet memory in a host memory accessible by the host processor; and

writing a completion queue entry (CQE) to the completion queue, wherein the completion queue is located in the host memory, and wherein the CQE corresponds to the memory location or a descriptor entry.

3. The network device of claim 2 , wherein updating the pointer includes updating a completion queue head pointer indicating a last CQE that has been processed by the host processor.

4. The network device of claim 3 , wherein the completion queue and a submission queue descriptor list have a one-to-one correspondence.

5. The network device of claim 2 , wherein the processing logic is further operable to:

read a descriptor entry in a submission queue descriptor list to determine the memory location to write the packet to.

6. The network device of claim 5 , wherein the submission queue descriptor list is in the host memory.

7. The network device of claim 5 , wherein the submission queue descriptor list is in a device memory of the network device.

8. The network device of claim 2 , wherein the interrupt is specific to the completion queue.

9. The network device of claim 2 , wherein the MMIO write transaction includes an interrupt delay value that sets a time delay between writing the CQE and sending the interrupt.

10. The network device of claim 1 , wherein the interrupt is a Message Signaled Interrupt-X (MSI-X).

11. The network device of claim 1 , wherein the bus is a PCI-based bus.

12. The network device of claim 1 , wherein the queue is in a memory block of a host memory, and wherein the memory block is reserved for a first virtual machine (VM) exectable by the host processor.

13. The network device of claim 12 , wherein the first VM is operable to initiate the MMIO write transaction.

14. The network device of claim 1 further comprising:

receiving a notification from the host processor that the packet is ready for transmission;

fetching the packet from a host memory; and

transmitting, by the network interface, the packet onto a network.

15. A method comprising:

receiving, by a network interface of a network device, a packet;

writing the packet to a memory location in a packet memory in a host memory accessible by a host processor;

writing a completion queue entry (CQE) to a completion queue in the host memory, wherein the CQE indicates the memory location in the packet memory;

sending an interrupt from the network device to the host processor;

receiving, by a bus interface of the network device, a Memory-Mapped Input/Output (MMIO) write transaction that includes a completion queue head pointer value and an interrupt unmasking value, the completion queue head pointer value indicating a last CQE in the completion queue in the host memory that has been processed by the host processor; and

unmasking the interrupt with the interrupt unmasking value.

16. The method of claim 15 , wherein the MMIO write transaction includes a second completion queue head pointer value, the completion queue head pointer value corresponding to the completion queue of a first virtual machine (VM) running on the host processor and the second completion queue head pointer value corresponding to a second completion queue of the first VM running on the host processor.

17. The method of claim 15 , wherein the MMIO write transaction includes an interrupt delay value that sets a time delay between writing the CQE and sending the interrupt.

18. The method of claim 15 , wherein the network device is a Network Interface Card (NIC).