IP Library Granted Patent US 10,122,537
Granted Patent B2
US 10,122,537 · App. 15/109,327 · Granted Nov 6, 2018

Apparatus and method for generating random digital value

Inventors: Dong Kyue Kim (Seoul, KR); Byong Deok Choi (Seoul, KR)
Assignee: ICTK HOLDINGS CO., LTD.
H04L9/3278G06F21/73G09C1/00H04L9/0866H04L2209/12
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Quick Facts
Patent No.
US 10,122,537
App. No.
15/109,327
Granted
Nov 6, 2018
Kind
B2
Abstract

Provided is an apparatus for generating digital values to provide a random digital value. The apparatus may generate the digital value based on a semiconductor process variation. The apparatus may include a generating unit to generate a plurality of digital values, based on the semiconductor process variation, and a processing unit to process the digital values and to provide a first digital value. The generating unit may include a plurality of physically unclonable functions (PUFs). A parameter may be differently applied to the PUFs, and the PUFs may generate the digital values.

Claims (24)

1. An apparatus for generating a digital value, the apparatus comprising:

a generating unit to generate a plurality of digital values, the generating unit comprising a plurality of physically unclonable functions (PUFs), wherein a portion of the PUFs is implemented by applying at least one parameter causing a semiconductor process variation; and

a processing unit to process the digital values and to provide a first digital value,

wherein at least one of the PUFs comprises a via formed between conductive layers in a semiconductor, and

wherein the parameter comprises a size of the via selected from a range between a minimum value and a maximum value of the size of the via corresponding to whether the via causes a short between the conductive layers.

2. The apparatus of claim 1 , wherein at least one of the digital values is generated based on whether the via causes a short between the conductive layers.

3. The apparatus of claim 1 , wherein the size of the via is determined prior to manufacturing the apparatus.

4. The apparatus of claim 1 , wherein the processing unit selects, as the first digital value among the digital values, a digital value that satisfies a condition.

5. The apparatus of claim 1 , wherein the processing unit selects, as the first digital value among the digital values, a value generated by a PUF in which the applied parameter has a minimum value, among a group of PUFs that each provides a digital value corresponding to a bit sequence including both “0” and “1.”

6. The apparatus of claim 1 , wherein the processing unit selects, as the first digital value among the digital values, a value generated by a PUF in which the applied parameter has a median value between a minimum value and a maximum value, among a group of PUFs that each provides a digital value corresponding to a bit sequence including both “0” and “1.”

7. The apparatus of claim 1 , wherein the processing unit performs a logical operation on the digital values for each bit sequence, and calculates the first digital value.

8. The apparatus of claim 7 , wherein the logical operation is an eXclusive OR (XOR) logical operation.

9. A method of generating a digital value by an apparatus for generating a digital value based on a semiconductor process variation, the method comprising:

generating, by a plurality of physically unclonable functions (PUFs), a plurality of digital values, a portion of the PUFs being manufactured by differently applying at least one parameter causing the semiconductor process variation; and

processing, by a processing unit, the digital values and providing a first digital value,

wherein at least one of the PUFs comprises a via formed between conductive layers in a semiconductor, and

wherein the parameter comprises a size of the via selected from a range between a minimum value and a maximum value of the size of the via corresponding to whether the via causes a short between the conductive layers.

10. The method of claim 9 , wherein the generating comprises generating at least one of the digital values based on whether the conductive layers are shorted by the via.

11. The method of claim 10 , wherein the size of the via is determined in a test process performed prior to a process of manufacturing the apparatus, and different via sizes in the range are applied to the PUFs.

12. The method of claim 9 , wherein the processing comprises selecting, as the first digital value among the digital values, a digital value that satisfies a condition.

13. The method of claim 12 , wherein the processing unit selects, as the first digital value among the digital values, a value generated by a PUF in which the applied parameter has a minimum value, among a group of PUFs that each provides a digital value corresponding to a bit sequence including both “0” and “1.”

14. The method of claim 12 , wherein the processing unit selects, as the first digital value among the digital values, a value generated by a PUF in which the applied parameter has a median value between a minimum value and a maximum value, among a group of PUFs that each provides a digital value corresponding to a bit sequence including both “0” and “1.”

15. The method of claim 9 , wherein the processing comprises performing a logical operation on the digital values for each bit sequence, and calculating the first digital value.

16. The method of claim 15 , wherein the logical operation is an eXclusive OR (XOR) logical operation.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 2, 2018
From: ICTK CO., LTD.
To: ICTK HOLDINGS CO., LTD.
Reel/Frame 047028/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2016
From: KIM, DONG KYUE; CHOI, BYONG DEOK
To: ICTK CO., LTD.
Reel/Frame 039107/0870 →
Priority Claims (1)
KR 10-2013-0168530 · Dec 31, 2013 · national
Continuity (1)
Related Publication 20160330038A1 · Nov 10, 2016