Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions
Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions are described. For example, a semiconductor structure includes a plurality of parallel semiconductor fins disposed above and continuous with a semiconductor substrate. An isolation structure is disposed above the semiconductor substrate and adjacent to lower portions of each of the plurality of parallel semiconductor fins. An upper portion of each of the plurality of parallel semiconductor fins protrudes above an uppermost surface of the isolation structure. Epitaxial source and drain regions are disposed in each of the plurality of parallel semiconductor fins adjacent to a channel region in the upper portion of the semiconductor fin. The epitaxial source and drain regions do not extend laterally over the isolation structure. The semiconductor structure also includes one or more gate electrodes, each gate electrode disposed over the channel region of one or more of the plurality of parallel semiconductor fins.
1. A semiconductor structure, comprising:
a plurality of parallel semiconductor fins disposed above and continuous with a semiconductor substrate;
an isolation structure disposed above the semiconductor substrate and adjacent to lower portions of each of the plurality of parallel semiconductor fins, wherein an upper portion of each of the plurality of parallel semiconductor fins protrudes above an uppermost surface of the isolation structure;
epitaxial source and drain regions disposed in each of the plurality of parallel semiconductor fins adjacent to a channel region in the upper portion of the semiconductor fin, wherein the epitaxial source and drain regions do not extend laterally over the isolation structure; and
one or more gate electrodes, each gate electrode disposed over the channel region of one or more of the plurality of parallel semiconductor fins.
2. The semiconductor structure of claim 1 , wherein respective source and drain regions of adjacent semiconductor fins are not merged with or in contact with one another.
3. The semiconductor structure of claim 1 , wherein the epitaxial source and drain regions are stress inducing for the respective channel region.
4. The semiconductor structure of claim 1 , further comprising:
a contact metal layer disposed on all surfaces of the epitaxial source and drain regions exposed above the uppermost surface of the isolation structure.
5. The semiconductor structure of claim 1 , wherein the epitaxial source and drain regions comprise a semiconductor material different than a semiconductor material of the channel regions of the plurality of semiconductor fins.
6. The semiconductor structure of claim 1 , wherein the epitaxial source and drain regions each have a bottom surface below the uppermost surface of the isolation structure.
7. The semiconductor structure of claim 1 , wherein the epitaxial source and drain regions each have a bottom surface approximately planar with the uppermost surface of the isolation structure.
8. The semiconductor structure of claim 1 , wherein the epitaxial source and drain regions each have a bottom surface above the uppermost surface of the isolation structure.