Instruction and logic for sorting and retiring stores
A processor includes logic to execute an instruction stream out-of-order. The instruction stream is divided into a plurality of strands and its instructions and those within the streams are ordered by program order (PO). The processor further includes logic to identify an oldest undispatched instruction in the instruction stream and record its associated PO as an executed instruction pointer, identify a most recently committed store instruction in the instruction stream and record its associated PO as a store commitment pointer, a search pointer with PO less than the execution instruction pointer, identify a first set of store instructions in a store buffer with PO less than the search pointer and eligible for commitment, evaluate whether the first set of store instructions is larger than a number of read ports of the store buffer, and adjust the search pointer.
1. A processor, comprising:
one or more execution units comprising circuitry to execute an instruction stream out-of-order, the instruction stream divided into a plurality of strands, the instruction stream and contents within each strand ordered by program order (PO); and
a memory system communicatively coupled to the one or more execution units, wherein the memory system comprises logic to:
identify an oldest undispatched instruction in the instruction stream and record its associated PO as an executed instruction pointer;
identify a most recently committed store instruction in the instruction stream and record its associated PO as a store commitment pointer;
determine a search pointer with PO less than the execution instruction pointer;
identify a first set of store instructions in a store buffer, each store instruction with PO less than the search pointer and eligible for commitment;
evaluate whether the first set of store instructions is larger than a number of read ports of the store buffer; and
adjust the search pointer based upon an evaluation that the first set of store instructions is larger than the number of read ports of the store buffer.
2. The processor of claim 1 , further comprising circuitry to:
identify a second set of store instructions, each store instruction with a PO less than the search pointer after the adjustment of the search pointer;
evaluate whether the second set of store instructions is larger than the number of read ports of the store buffer; and
commit the second set of store instructions based upon an evaluation that the second set of store instructions is smaller than or equal in size to the number of read ports of the store buffer.
3. The processor of claim 2 , further comprising circuitry to sort the second set of store instructions according to PO before the second set of store instructions is committed.
4. The processor of claim 2 , further comprising circuitry to write a store buffer identifier of each of the second set of store instructions to a store retirement queue to commit the second set of store instructions.
5. The processor of claim 1 , further comprising circuitry to adjust the search pointer based upon the size of the first set of store instructions.
6. The processor of claim 1 , further comprising circuitry to adjust the search pointer based upon the size of the first set of store instructions and the number of read ports of the store buffer.
7. The processor of claim 1 , further comprising circuitry to adjust the search pointer based upon a previous adjustment to the search pointer.
8. A method comprising, within a processor:
executing an instruction stream out-of-order, the instruction stream divided into a plurality of strands, the instruction stream and contents within each strand ordered by program order (PO);
identifying an oldest undispatched instruction in the instruction stream and recording its associated PO as an executed instruction pointer;
identifying a most recently committed store instruction in the instruction stream and recording its associated PO as a store commitment pointer;
determining a search pointer with PO less than the execution instruction pointer;
identifying a first set of store instructions in a store buffer, each store instruction with PO less than the search pointer and eligible for commitment;
evaluating whether the first set of store instructions is larger than a number of read ports of the store buffer; and
adjusting the search pointer based upon an evaluation that the first set of store instructions is larger than the number of read ports of the store buffer.
9. The method of claim 8 , further comprising:
identifying a second set of store instructions, each store instruction with a PO less than the search pointer after adjusting the search pointer;
evaluating whether the second set of store instructions is larger than the number of read ports of the store buffer; and
committing the second set of store instructions based upon an evaluation that the second set of store instructions is smaller than or equal in size to the number of read ports of the store buffer.
10. The method of claim 9 , further comprising sorting the second set of store instructions according to PO before the second set of store instructions is committed.
11. The method of claim 8 , further comprising writing a store buffer identifier of each of the second set of store instructions to a store retirement queue to commit the second set of store instructions.
12. The method of claim 8 , further comprising adjusting the search pointer based upon the size of the first set of store instructions.
13. The method of claim 8 , further comprising adjusting the search pointer based upon the size of the first set of store instructions and the number of read ports of the store buffer.
14. A system comprising:
a processor comprising:
one or more execution units comprising circuitry to execute an instruction stream out-of-order, the instruction stream divided into a plurality of strands, the instruction stream and contents within each strand ordered by program order (PO); and
a memory system communicatively coupled to the one or more execution units, wherein the memory system comprises logic to:
identify an oldest undispatched instruction in the instruction stream and record its associated PO as an executed instruction pointer;
identify a most recently committed store instruction in the instruction stream and record its associated PO as a store commitment pointer;
determine a search pointer with PO less than the execution instruction pointer;
identify a first set of store instructions in a store buffer, each store instruction with PO less than the search pointer and eligible for commitment;
evaluate whether the first set of store instructions is larger than a number of read ports of the store buffer; and
adjust the search pointer based upon an evaluation that the first set of store instructions is larger than the number of read ports of the store buffer.
15. The system of claim 14 , further comprising circuitry to:
identify a second set of store instructions, each store instruction with a PO less than the search pointer after the adjustment of the search pointer;
evaluate whether the second set of store instructions is larger than the number of read ports of the store buffer; and
commit the second set of store instructions based upon an evaluation that the second set of store instructions is smaller than or equal in size to the number of read ports of the store buffer.
16. The system of claim 15 , further comprising circuitry to sort the second set of store instructions according to PO before the second set of store instructions is committed.
17. The system of claim 15 , further comprising circuitry to write a store buffer identifier of each of the second set of store instructions to a store retirement queue to commit the second set of store instructions.
18. The system of claim 14 , further comprising circuitry to adjust the search pointer based upon the size of the first set of store instructions.
19. The system of claim 14 , further comprising circuitry to adjust the search pointer based upon the size of the first set of store instructions and the number of read ports of the store buffer.
20. The system of claim 14 , further comprising circuitry to adjust the search pointer based upon a previous adjustment to the search pointer.