Array substrate and liquid crystal display apparatus having the same
An array substrate and a liquid crystal display apparatus are disclosed. The array substrate includes: a glass substrate; a light-shielding metallic layer mounted having a first region and a second region; a first insulating layer; a thin-film transistor; a pixel electrode layer; a common electrode layer electrically connected to the light-shielding metallic layer. A storage capacitor is formed between the second region and a drain electrode of the thin-film transistor. The array substrate has an advantage of increasing the storage capacitance of liquid crystal display apparatus and therefore enhancing display performance.
1. An array substrate, comprising:
a glass substrate;
a light-shielding metallic layer mounted on the glass substrate, and the light-shielding layer has a first region and a second region;
a first insulating layer mounted on the glass substrate and the light-shielding metallic layer;
a thin-film transistor mounted on the first insulating layer, and the thin-film transistor has a source electrode, a drain electrode, a gate electrode and a semiconductor layer;
a pixel electrode layer electrically connected to the drain electrode;
a common electrode layer electrically connected to the light-shielding metallic layer, wherein a first storage capacitor is formed between the pixel electrode layer and the common electrode layer; wherein
the first region of the light-shielding metallic layer is used to block light; the second region of the light-shielding layer directly faces the drain electrode so as to form a second storage capacitor between the second region of the light-shielding layer and the drain electrode; wherein
a flattening layer is mounted on the thin-film transistor; the common electrode layer is mounted on the flattening layer; a third insulating layer is mounted on the common electrode layer; the pixel electrode layer is mounted on the third insulating layer; wherein
the thin-film transistor further includes a second insulating layer and an interlayer dielectric layer; the semiconductor layer is mounted on the first insulating layer; the source electrode is mounted on the first insulating layer and the semiconductor layer; the drain electrode is mounted on the first insulating layer and the semiconductor layer; the second insulating layer is mounted on the source electrode, the drain electrode, the semiconductor layer and the first insulating layer; the gate electrode is mounted on the second insulating layer; the interlayer dielectric layer is mounted on the gate electrode and the second insulating layer; the flattening layer is mounted on the interlayer dielectric layer; wherein
a second metallic layer is mounted on the first insulating layer and the semiconductor layer; the second metallic layer has a source region, a drain region and a connection region which are insulated from each other; the flattening layer, the interlayer dielectric layer and the second insulating layer are sequentially penetrated to form a fifth through hole; the common electrode is in contact with and electrically connected to the connection region of the second metallic layer through the fifth through hole; the connection region of the second metallic layer is electrically connected to the light-shielding metallic layer.
2. The array substrate as claimed in claim 1 , herein a third through hole is formed through the first insulating layer; the connection region of the second metallic layer is in contact with and electrically connected to the light-shielding metallic layer through the third through hole.
3. A liquid crystal display apparatus, comprising the array substrate as claimed in claim 1 .
4. An array substrate, comprising:
a glass substrate;
a light-shielding metallic layer mounted on the glass substrate, and the light-shielding layer has a first region and a second region;
a first insulating layer mounted on the glass substrate and the light-shielding metallic layer;
a thin-film transistor mounted on the first insulating layer, and the thin-film transistor has a source electrode, a drain electrode, a gate electrode and a semiconductor layer;
a pixel electrode layer electrically connected to the drain electrode;
a common electrode layer electrically connected to the light-shielding metallic layer, wherein a first storage capacitor is formed between the pixel electrode layer and the common electrode layer;
the first region of the light-shielding metallic layer is used to block light; the second region of the light-shielding layer directly faces the drain electrode so as to form a second storage capacitor between the second region of the light-shielding layer and the drain electrode;
a flattening layer is mounted on the thin-film transistor; the common electrode layer is mounted on the flattening layer; a third insulating layer is mounted on the common electrode layer; the pixel electrode layer is mounted on the third insulating layer;
the thin-film transistor further includes a second insulating layer and an interlayer dielectric layer; the semiconductor layer is mounted on the first insulating layer; the second insulating layer is mounted on the semiconductor layer; the gate electrode is mounted on the second insulating layer; the interlayer dielectric layer is mounted on the second insulating layer and the gate electrode; the source electrode and the drain electrode are mounted on the interlayer dielectric layer; the flattening layer is disposed on the source electrode, the drain electrode and the interlayer dielectric layer;
the source electrode is in contact with the semiconductor layer by extending through a first through hole of the interlayer dielectric layer and a first through hole of the second insulating layer; the drain electrode is in contact with the semiconductor layer by extending through a second through hole of the interlayer dielectric layer and a second through hole of the second insulating layer;
a second metallic layer is mounted on the second insulating layer; the second metallic layer has a source region, a drain region and a connection region which are insulated from each other;
the source electrode is mounted on the source region of the second metallic layer; the drain electrode is mounted on the drain region of the second metallic layer; the flattening layer has a fourth through hole; the common electrode is in contact with and electrically connected to the connection region of the second metallic layer through the fourth through hole; the connection region of the second metallic layer is electrically connected to the light-shielding metallic layer;
the second insulating layer and the first insulating layer are sequentially penetrated to form a third through hole therethrough; the connection region of the second metallic layer is in contact with and electrically connected to the light-shielding metallic layer through the third through hole.
5. An array substrate, comprising:
a glass substrate;
a light-shielding metallic layer mounted on the glass substrate, and the light-shielding layer has a first region and a second region;
a first insulating layer mounted on the glass substrate and the light-shielding metallic layer;
a thin-film transistor mounted on the first insulating layer, and the thin-film transistor has a source electrode, a drain electrode, a gate electrode and a semiconductor layer;
a pixel electrode layer electrically connected to the drain electrode;
a common electrode layer electrically connected to the light-shielding metallic layer, wherein a first storage capacitor is formed between the pixel electrode layer and the common electrode layer;
the first region of the light-shielding metallic layer is used to block light; the second region of the light-shielding layer directly faces the drain electrode so as to form a second storage capacitor between the second region of the light-shielding layer and the drain electrode;
a flattening layer is mounted on the thin-film transistor; the common electrode layer is mounted on the flattening layer; a third insulating layer is mounted on the common electrode layer; the pixel electrode layer is mounted on the third insulating layer;
the thin-film transistor further includes a second insulating layer and an interlayer dielectric layer; the semiconductor layer is mounted on the first insulating layer; the second insulating layer is mounted on the semiconductor layer; the gate electrode is mounted on the second insulating layer; the interlayer dielectric layer is mounted on the second insulating layer and the gate electrode; the source electrode and the drain electrode are mounted on the interlayer dielectric layer; the flattening layer is disposed on the source electrode, the drain electrode and the interlayer dielectric layer;
the source electrode is in contact with the semiconductor layer by extending through a first through hole of the interlayer dielectric layer and a first through hole of the second insulating layer; the drain electrode is in contact with the semiconductor layer by extending through a second through hole of the interlayer dielectric layer and a second through hole of the second insulating layer;
a second metallic layer is mounted on the second insulating layer; the second metallic layer has a source region, a drain region and a connection region which are insulated from each other;
the source electrode is mounted on the source region of the second metallic layer; the drain electrode is mounted on the drain region of the second metallic layer; the flattening layer has a fourth through hole; the common electrode is in contact with and electrically connected to the connection region of the second metallic layer through the fourth through hole; the connection region of the second metallic layer is electrically connected to the light-shielding metallic layer.