IP Library › Granted Patent US 11,139,248
Granted Patent B2
US 11,139,248 · App. 15/128,443 · Granted Oct 5, 2021

Mounting substrate and electronic apparatus

Inventor: Akiyoshi Aoyagi (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H01L23/5386H01L21/486H01L21/4853H01L21/4857H01L23/5383H01L23/5384H01L25/167H01L31/02005H01L33/62H01L2924/0002H05K1/185H05K3/4602H05K2201/10106H05K2201/10128
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Quick Facts
Patent No.
US 11,139,248
App. No.
15/128,443
Granted
Oct 5, 2021
Kind
B2
Abstract

A mounting substrate according to an embodiment of the present technology includes: a wiring substrate ( 30 ); a fine L/S layer ( 40 ) formed in contact with a top surface of the wiring substrate; and a plurality of elements ( 12, 13 ) arranged in a matrix on a top surface of the fine L/S layer. The wiring substrate includes a plurality of first wiring lines (SigB 1 , Gate 2 ), and a plurality of vias ( 14 ) arranged at a period corresponding to an integral multiple of an arrangement period of the plurality of element, and two or more of the vias are provided for each of the first wiring lines. Two or more adjacent ones of the elements on the fine L/S layer are electrically coupled to common one of the vias through one or more second wiring lines ( 16 ).

Claims (44)

1. A mounting substrate, comprising:

a wiring substrate;

a fine line layer formed in contact with a top surface of the wiring substrate;

a plurality of elements arranged in a matrix on a top surface of the fine line layer, wherein the plurality of elements each include a light-emitting element and a drive circuit that drives the light-emitting element, and wherein the light-emitting element and the drive circuit are mounted directly on the top surface of the fine line layer;

a light-transmissive embedding layer formed over the fine line layer and the plurality of elements; and

a light-shielding layer formed over the light-transmissive embedding layer, the light-shielding layer having an opening facing each light-emitting element,

wherein the wiring substrate includes:

a plurality of first wiring lines extending in a predetermined direction in a layer, and

a plurality of vias arranged at a period corresponding to an integral multiple of an arrangement period of the plurality of elements, two or more of the plurality of vias being provided for each of the plurality of first wiring lines,

the fine line layer includes:

a plurality of second wiring lines, one or more of the plurality of second wiring lines being provided for each of the plurality of vias, and

an insulating layer provided between each of the plurality of second wiring lines and the top surface of the wiring substrate, and being in contact with each of the plurality of second wiring lines and the top surface of the wiring substrate,

a wiring pitch of the fine line layer is smaller than a wiring pitch of at least one of the plurality of first wiring lines, and

two or more adjacent ones of the plurality of elements are electrically coupled to a common one of the plurality of vias through the one or more of the plurality of second wiring lines.

2. The mounting substrate according to claim 1 , wherein the plurality of first wiring lines extend in a row direction or a column direction,

the plurality of vias are arranged at the period corresponding to the integral multiple of the arrangement period of the plurality of elements in an extending direction of the plurality of first wiring lines, and

the plurality of elements aligned in the extending direction of the plurality of first wiring lines are electrically coupled to the common one of the plurality of vias through the one or more of the plurality of second wiring lines.

3. The mounting substrate according to claim 2 , wherein the plurality of vias are formed on or above the plurality of second wiring lines, and exposed on the top surface of the wiring substrate.

4. The mounting substrate according to claim 3 , wherein the wiring substrate includes a plurality of electrode pads exposed on a rear surface of the wiring substrate, one or more of the plurality of electrode pads being provided for each of the plurality of first wiring lines.

5. The mounting substrate according to claim 4 , wherein each of the plurality of second wiring lines is bonded by plating to the plurality of via or a member electrically coupled to the plurality of via, and is further bonded by plating to each of the plurality of elements.

6. The mounting substrate according to claim 5 , wherein the wiring substrate is a build-up substrate including a core substrate and one or more build-up layers formed on each of both sides of the core substrate,

the plurality of vias are formed at least in the one or more build-up layers on the top surface of the wiring substrate, and

the plurality of electrode pads are formed at least in the one or more build-up layers on the rear surface of the wiring substrate.

7. An electronic apparatus, comprising:

one or a plurality of mounting substrates; and

a control circuit that controls the one or plurality of mounting substrates,

wherein the one or the plurality of mounting substrate each includes:

a wiring substrate,

a fine line layer formed in contact with a top surface of the wiring substrate,

a plurality of elements arranged in a matrix on a top surface of the fine line layer, wherein the plurality of elements each include a light-emitting element and a drive circuit that drives the light-emitting element, and wherein the light-emitting element and the drive circuit are mounted directly on the top surface of the fine line layer,

a light-transmissive embedding layer formed over the fine line layer and the plurality of elements, and

a light-shielding layer formed over the light-transmissive embedding layer, the light-shielding layer having an opening facing each light-emitting element,

wherein the wiring substrate of the one or a plurality of mounting substrates each includes:

a plurality of first wiring lines extending in a predetermined direction in a layer, and

a plurality of vias arranged at a period corresponding to an integral multiple of an arrangement period of the plurality of elements, two or more of the plurality of vias being provided for each of the plurality of first wiring lines,

the fine line layer of the one or a plurality of mounting substrates each includes:

a plurality of second wiring lines, one or more of the plurality of second wiring lines being provided for each of the plurality of vias, and

an insulating layer provided between each of the plurality of second wiring lines and the top surface of the wiring substrate, and being in contact with each of the plurality of second wiring lines and the top surface of the wiring substrate,

a wiring pitch of the fine line layer is smaller than a wiring pitch of at least one of the plurality of first wiring lines, and

two or more adjacent ones of the plurality of elements are electrically coupled to a common one of the plurality of vias through the one or more of the plurality of second wiring lines.

8. The electronic apparatus according to claim 7 , further comprising:

a supporting substrate that supports the one or a plurality of mounting substrates; and

a control substrate that controls the one or a plurality of mounting substrates, wherein the one or a plurality of mounting substrates are tiled on the supporting substrate,

the wiring substrate of the one or a plurality of mounting substrates each include a plurality of electrode pads exposed on a rear surface of the wiring substrate, one or more of the plurality of electrode pads being provided for each of the plurality of first wiring lines, and one or both of the supporting substrate and the control substrate are electrically coupled to each wiring substrate through each of the plurality of electrode pads.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2017
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 043546/0060 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2016
From: AOYAGI, AKIYOSHI
To: SONY CORPORATION
Reel/Frame 040232/0869 →
Priority Claims (1)
JP JP2014-074844 · Mar 31, 2014 · national
Continuity (1)
Related Publication 20180174973A1 · Jun 21, 2018