Integrated structures comprising vertical channel material and having conductively-doped semiconductor material directly against lower sidewalls of the channel material
Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.
1. An integrated structure, comprising:
vertically-stacked conductive levels; upper conductive levels of the vertically-stacked conductive levels being memory cell levels, and a lower conductive level of the vertically-stacked conductive levels being a select device level;
a conductively-doped semiconductor material under the select device level, and spaced from the select device level by an insulative region;
a channel material extending vertically along the memory cell levels and the select device level, and extending downwardly into the conductively-doped semiconductor material; a region of the channel material that extends into the conductively-doped semiconductor material being a lower region of the channel material and having a vertical sidewall;
a tunneling material, a charge-storage material and a charge-blocking material extending vertically along the channel material and being between the channel material and the vertically-stacked conductive levels;
the tunneling material, charge-storage material and charge-blocking material not being along at least a portion of the vertical sidewall of said lower region of the channel material; the conductively-doped semiconductor material being directly against said portion of the vertical sidewall of the lower region of the channel material; and
wherein the conductively-doped semiconductor material is a second conductively-doped semiconductor material, and is over and directly against a first conductively-doped semiconductor material; wherein the channel material extends downwardly into the first and second conductively-doped semiconductor materials, and directly contacts both of the first and second conductively-doped semiconductor materials; and wherein the first and second conductively-doped semiconductor materials are compositionally different from one another.
2. The integrated structure of claim 1 including a region of the first conductively-doped semiconductor material between the second conductively-doped semiconductor material and the select device level.
3. An integrated structure, comprising:
vertically-stacked conductive levels; upper conductive levels of the vertically-stacked conductive levels being memory cell levels, and a lower conductive level of the vertically-stacked conductive levels being a select device level;
a conductively-doped semiconductor material under the select device level, and spaced from the select device level by an insulative region;
a channel material extending vertically along the memory cell levels and the select device level, and extending downwardly into the conductively-doped semiconductor material; a region of the channel material that extends into the conductively-doped semiconductor material being a lower region of the channel material and having a vertical sidewall;
a tunneling material, a charge-storage material and a charge-blocking material extending vertically along the channel material and being between the channel material and the vertically-stacked conductive levels;
the tunneling material, charge-storage material and charge-blocking material not being along at least a portion of the vertical sidewall of said lower region of the channel material; the conductively-doped semiconductor material being directly against said portion of the vertical sidewall of the lower region of the channel material; and
wherein a metal-containing material is under the conductively-doped semiconductor material and under the channel material; and wherein the conductively-doped semiconductor material and the channel material are both directly against the metal-containing material.
4. An integrated structure, comprising:
vertically-stacked conductive levels; upper conductive levels of the vertically-stacked conductive levels being memory cell levels, and a lower conductive level of the vertically-stacked conductive levels being a select device level;
a conductively-doped semiconductor material under the select device level, and spaced from the select device level by an insulative region;
a channel material extending vertically along the memory cell levels and the select device level, and extending downwardly into the conductively-doped semiconductor material; a region of the channel material that extends into the conductively-doped semiconductor material being a lower region of the channel material and having a vertical sidewall;
a tunneling material, a charge-storage material and a charge-blocking material extending vertically along the channel material and being between the channel material and the vertically-stacked conductive levels;
the tunneling material, charge-storage material and charge-blocking material not being along at least a portion of the vertical sidewall of said lower region of the channel material; the conductively-doped semiconductor material being directly against said portion of the vertical sidewall of the lower region of the channel material; and
wherein said portion of the vertical sidewall of the lower region of the channel material is above a lowest region of the channel material; and wherein the tunneling material, charge-storage material and charge-blocking material are along the lowest region.
5. An integrated structure, comprising:
vertically-stacked conductive levels; upper conductive levels of the vertically-stacked conductive levels being memory cell levels, and a lower conductive level of the vertically-stacked conductive levels being a select device level; the vertically-stacked conductive levels being configured as two laterally spaced sets along a cross-section; the sets being a first set and a second set; a conductive pillar being between the first and second sets;
a conductively-doped semiconductor material under the select device levels of the first and second sets; the conductive pillar extending to the conductively-doped semiconductor material and being in electrical contact with the conductively-doped semiconductor material;
a first channel material extending vertically along the memory cell levels and the select device level of the first set, and extending downwardly into the conductively-doped semiconductor material; a region of the first channel material that extends into the conductively-doped semiconductor material being a first lower region of the first channel material and having a first vertical sidewall;
a second channel material extending vertically along the memory cell levels and the select device level of the second set, and extending downwardly into the conductively-doped semiconductor material; a region of the second channel material that extends into the conductively-doped semiconductor material being a second lower region of the second channel material and having a second vertical sidewall;
the conductively-doped semiconductor material being directly against the first and second vertical sidewalls; and
wherein the conductively-doped semiconductor material is a second conductively-doped semiconductor material, and is over and directly against a first conductively-doped semiconductor material; wherein the first and second channel materials extend downwardly into the first and second conductively-doped semiconductor materials, and directly contact both of the first and second conductively-doped semiconductor materials; and wherein the first and second conductively-doped semiconductor materials are compositionally different from one another.
6. An integrated structure, comprising:
vertically-stacked conductive levels; upper conductive levels of the vertically-stacked conductive levels being memory cell levels, and a lower conductive level of the vertically-stacked conductive levels being a select device level; the vertically-stacked conductive levels being configured as two laterally spaced sets along a cross-section; the sets being a first set and a second set; a conductive pillar being between the first and second sets;
a conductively-doped semiconductor material under the select device levels of the first and second sets; the conductive pillar extending to the conductively-doped semiconductor material and being in electrical contact with the conductively-doped semiconductor material;
a first channel material extending vertically along the memory cell levels and the select device level of the first set, and extending downwardly into the conductively-doped semiconductor material; a region of the first channel material that extends into the conductively-doped semiconductor material being a first lower region of the first channel material and having a first vertical sidewall;
a second channel material extending vertically along the memory cell levels and the select device level of the second set, and extending downwardly into the conductively-doped semiconductor material; a region of the second channel material that extends into the conductively-doped semiconductor material being a second lower region of the second channel material and having a second vertical sidewall;
the conductively-doped semiconductor material being directly against the first and second vertical sidewalls; and
wherein a first metal-containing material is directly under the first set, and a second metal-containing material is directly under the second set; wherein the first and second channel materials are directly against the first and second metal-containing materials, respectively; and wherein the conductively-doped semiconductor material is directly against the first and second metal-containing materials.
7. The integrated structure of claim 6 comprising a semiconductor material region laterally between the first and second metal-containing materials and directly under the conductive pillar.
8. An integrated structure, comprising:
vertically-stacked conductive levels; upper conductive levels of the vertically-stacked conductive levels being memory cell levels, and a lower conductive level of the vertically-stacked conductive levels being a select device level; the vertically-stacked conductive levels being configured as two laterally spaced sets along a cross-section; the sets being a first set and a second set; a conductive pillar being between the first and second sets;
a conductively-doped semiconductor material under the select device levels of the first and second sets; the conductive pillar extending to the conductively-doped semiconductor material and being in electrical contact with the conductively-doped semiconductor material;
a first channel material extending vertically along the memory cell levels and the select device level of the first set, and extending downwardly into the conductively-doped semiconductor material; a region of the first channel material that extends into the conductively-doped semiconductor material being a first lower region of the first channel material and having a first vertical sidewall;
a second channel material extending vertically along the memory cell levels and the select device level of the second set, and extending downwardly into the conductively-doped semiconductor material; a region of the second channel material that extends into the conductively-doped semiconductor material being a second lower region of the second channel material and having a second vertical sidewall;
the conductively-doped semiconductor material being directly against the first and second vertical sidewalls; and
wherein the first and second vertical sidewalls directly against the conductively-doped semiconductor material are above lowest regions of the first and second channel materials; and wherein a tunneling material, a charge-storage material and a charge-blocking material are along the lowest regions of the first and second channel materials.