Imaging device and electronic device

1. An imaging device comprising: pixels arranged in a matrix; and an Analog digital (A/D) converter circuit, wherein the A/D converter circuit comprises: a first circuit; a second circuit; a third circuit; and a fourth circuit, wherein the pixels are electrically connected to the first circuit, wherein the first circuit, the second circuit, the third circuit, and the fourth circuit are each configured to receive and send a high-level potential signal or a low-level potential signal, wherein the first circuit is configured to stop operating in response to a first signal, wherein the first circuit is configured to make a comparison between a second signal output from one of the pixels and a third signal serving as a reference potential signal and then output a fourth signal, wherein the second circuit is configured to output a seventh signal determined by a combination of the fourth signal, a fifth signal for controlling the fourth circuit, and a sixth signal for controlling the second circuit, wherein the third circuit is configured to stop outputting a clock signal in response to the seventh signal, and wherein the fourth circuit is configured to perform counting in response to the clock signal and output data of the counting.

2. The imaging device according to claim 1 ,

wherein the first circuit is a comparator circuit, and

wherein the fourth circuit is a counter circuit.

3. The imaging device according to claim 1 ,

wherein the pixels are each configured to hold first imaging data and to obtain differential data between the first imaging data and second imaging data.

4. The imaging device according to claim 1 ,

wherein the first circuit operates when the first signal has a high-level potential, and the first circuit stops operating when the first signal has a low-level potential.

5. The imaging device according to claim 1 ,

wherein the fourth signal output from the first circuit has a high-level potential when the first signal has the high-level potential and the second signal has a higher potential than the third signal,

wherein the fourth signal output from the first circuit has a low-level potential when the first signal has the high-level potential and the second signal has a lower potential than the third signal, and

wherein the fourth signal output from the first circuit has the low-level potential when the first signal has the low-level potential.

6. The imaging device according to claim 1 ,

wherein the seventh signal output from the second circuit has a high-level potential when the sixth signal has a high-level potential and the fifth signal and the fourth signal each have a high-level potential or each have a low-level potential,

wherein the seventh signal output from the second circuit has a low-level potential when the sixth signal has the high-level potential, one of the fifth signal and the fourth signal has the high-level potential, and the other of the fifth signal and the fourth signal has the low-level potential, and

wherein the seventh signal output from the second circuit has the low-level potential when the sixth signal has a low-level potential.

7. The imaging device according to claim 1 ,

wherein the sixth signal has the low-level potential when the first signal has the low-level potential.

8. The imaging device according to claim 1 ,

wherein the third circuit is configured to output the clock signal when the seventh signal has the high-level potential, and

wherein the third circuit is configured to stop outputting the clock signal when the seventh signal has the low-level potential.

9. The imaging device according to claim 1 ,

wherein the fourth circuit performs an addition operation when the fifth signal has the high-level potential, and

wherein the fourth circuit performs a subtraction operation when the fifth signal has the low-level potential.

10. The imaging device according to claim 1 ,

wherein each of the pixels comprises:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a first capacitor;

a second capacitor; and

a photoelectric conversion element,

wherein one of electrodes of the photoelectric conversion element is electrically connected to one of a source electrode and a drain electrode of the first transistor,

wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor,

wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to one of electrodes of the first capacitor,

wherein the other of the electrodes of the first capacitor is electrically connected to one of a source electrode and a drain electrode of the third transistor,

wherein the other of the electrodes of the first capacitor is electrically connected to a gate electrode of the fourth transistor,

wherein the other of the electrodes of the first capacitor is electrically connected to one of electrodes of the second capacitor,

wherein one of a source electrode and a drain electrode of the fourth transistor is electrically connected to one of a source electrode and a drain electrode of the fifth transistor, and

wherein the other of the source electrode and the drain electrode of the fifth transistor is electrically connected to the first circuit.

11. The imaging device according to claim 10 ,

wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor each include an oxide semiconductor in an active layer,

wherein the oxide semiconductor contains In, Zn, and M, and

wherein M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf.

12. The imaging device according to claim 10 ,

wherein the photoelectric conversion element includes selenium or a compound containing selenium in a photoelectric conversion layer.

13. An electronic device comprising:

the imaging device according to claim 1 ; and

a display device.

14. An imaging device comprising:

a pixel; and

an Analog digital (A/D) converter circuit,

wherein the A/D converter circuit comprises:

a first circuit;

a second circuit;

a third circuit; and

a fourth circuit,

wherein the pixel is electrically connected to the first circuit,

wherein the first circuit is configured to stop operating in response to a first signal,

wherein the first circuit is configured to output a fourth signal in response to a second signal output from the pixel and a third signal serving as a reference potential signal,

wherein the second circuit is configured to output a seventh signal in response to the fourth signal, a fifth signal for controlling the fourth circuit, and a sixth signal for controlling the second circuit,

wherein the third circuit is configured to stop outputting a clock signal in response to the seventh signal, and

wherein the fourth circuit is configured to perform counting in response to the clock signal and output data of the counting.

15. The image device according to claim 14 ,

wherein the first circuit is a comparator circuit, and

wherein the fourth circuit is a counter circuit.