Memory as a programmable logic device
Methods for operating memory cells include applying a respective minterm, comprising a plurality of variables, to control gates of series strings of memory cells, each series string programmed as a plurality of pairs of complementary memory cells such that certain ones of the plurality of variables are enabled, and logically combining each of the minterms into a logic function output. Memories include a plurality of memory cells configured in series strings of memory cells, wherein each series string of memory cells is configured to provide a minterm comprising a plurality of variables, each variable enabled responsive to a state of an associated, respective memory cell.
1. A method for operating memory cells, the method comprising:
applying a respective minterm, comprising a plurality of variables, to control gates of a plurality of series strings of memory cells, each series string of memory cells of the plurality of series strings of memory cells programmed as a plurality of pairs of complementary memory cells such that certain ones of the plurality of variables are enabled; and
logically combining each of the minterms into a logic function output;
wherein each series string of memory cells of the plurality of series strings of memory cells is selectively coupled to a same data line through a respective first select gate and each series string of memory cells of the plurality of series strings of memory cells is selectively coupled to a source through a respective second select gate.
2. The method of claim 1 , further comprising selectively enabling the series strings of memory cells of the plurality of series strings of memory cells to be logically combined into the logic function output.
3. The method of claim 2 , wherein selectively enabling a series strings of memory cells of the plurality of series strings of memory cells comprises enabling the first select gate of the series string of memory cells to be enabled.
4. The method of claim 1 , wherein logically combining comprises selectively coupling each series string of memory cells of the plurality of series strings of memory cells to the data line.
5. The method of claim 1 , wherein logically combining comprises logically ORing enabled series strings of memory cells of the plurality of series strings of memory cells.
6. The method of claim 1 , wherein do not care data is provided in a particular minterm responsive to an erased pair of complementary memory cells of a series strings of memory cells of the plurality of series strings of memory cells.
7. The method of claim 1 , further comprising enabling a particular variable with a programmed memory cell and disabling the particular variable with an erased memory cell.
8. A memory comprising:
a plurality of memory cells configured in series strings of memory cells wherein each series string of memory cells of the plurality of memory cells is configured to provide a minterm comprising a plurality of variables, each variable enabled responsive to a state of an associated, respective memory cell;
wherein each series string of memory cells of the plurality of memory cells is selectively coupled to a same data line of the memory through a respective first select gate and each series string of memory cells of the plurality of memory cells is selectively coupled to a source of the memory through a respective second select gate.
9. The memory of claim 8 , wherein the series strings of memory cells of the plurality of memory cells are selectively coupled to the data line such that a provided logic function comprises the minterm of each coupled series string of memory cells of the plurality of memory cells.
10. The memory of claim 9 , wherein the series strings of memory cells of the plurality of memory cells are all part of a memory block of the memory.
11. The memory of claim 10 , wherein the series strings of memory cells of the plurality of memory cells are each coupled to receive a same set of voltages at control gates of their respective memory cells.
12. The memory of claim 9 , wherein the respective first select gate of each series string of memory cells of the plurality of memory cells is a select gate drain transistor.
13. A memory comprising:
a first plurality of memory cells configured in series strings of memory cells wherein each series string of memory cells of the first plurality of memory cells is configured to provide a minterm comprising a plurality of variables, each variable enabled responsive to a state of an associated, respective memory cell;
a second plurality of memory cells configured in series strings of memory cells wherein each series string of memory cells of the second plurality of memory cells is configured to provide a minterm comprising a plurality of variables, each variable enabled responsive to a state of an associated, respective memory cell;
wherein each series string of memory cells of the first plurality of memory cells is selectively coupled to a particular data line of the memory;
wherein each series string of memory cells of the second plurality of memory cells is selectively coupled to a respective data line of the memory other than the particular data line; and
wherein, for each series string of memory cells of the first plurality of memory cells, a particular memory cell of that series string of memory cells has a control gate coupled to receive output of one of the respective data lines of the series strings of memory cells of the second plurality of memory cells.
14. The memory of claim 13 , wherein the series strings of memory cells of the first plurality of memory cells are each coupled to receive a same set of voltages at control gates of their respective remaining memory cells.
15. The memory of claim 13 , wherein the series strings of memory cells of the first plurality of memory cells are all part of a same memory block of the memory.
16. The memory of claim 15 , wherein the series strings of memory cells of the second plurality of memory cells are each part of a different respective memory block of the memory.
17. The memory of claim 15 , wherein the series strings of memory cells of the second plurality of memory cells are all part of a same memory block of the memory.
18. The memory of claim 13 , wherein do not care data is provided in a particular minterm of the first plurality of memory cells responsive to an erased pair of complementary memory cells of a series strings of memory cells of the first plurality of series strings of memory cells.
19. The memory of claim 13 , wherein do not care data is provided in a particular minterm of the second plurality of memory cells responsive to an erased pair of complementary memory cells of a series strings of memory cells of the second plurality of series strings of memory cells.
20. The memory of claim 13 , wherein the particular memory cell of one series string of memory cells of the first plurality of memory cells and the particular memory cell of a different series string of memory cells of the first plurality of memory cells each have their control gates coupled to receive the output of a same respective data line of series string of memory cells of the second plurality of memory cells.