Vertical memory structure with array interconnects and method for producing the same
Disclosed herein is a method and apparatus for fabricating a memory device. The memory device has a vertical stack of alternating layers of conductive and insulating layers wherein a top layer and a bottom layer are insulating layers. A plurality of vias is formed through the vertical stack from the top layer to the bottom layer. A memory layer disposed adjacent the conductive layers in the vias. A selector device disposed adjacent the memory layer wherein the selector device comprises multiple layers of dissimilar metal oxides. A lateral electrical contact to the memory layer through the conductive layer. And a top contact electrically connected to the conductive layer through a portion of the memory layer and the portion of the memory layer wherein the portion of the memory layer is configured to store data therein.
1. A memory device, comprising:
a vertical stack of alternating layers of conductive and insulating layers wherein a top layer and a bottom layer are insulating layers;
a plurality of vias disposed through the vertical stack from the top layer to the bottom layer;
a memory layer disposed adjacent the conductive layers in the vias;
a selector device disposed adjacent the memory layer, wherein the selector device comprises multiple layers of dissimilar metal oxides;
a lateral electrical contact to the memory layer; and
a top contact electrically connected to the conductive layer through a portion of the memory layer and the portion of the memory layer is configured to store data therein.
2. The memory device of claim 1 wherein the multiple layers of dissimilar metal oxides comprises:
a first layer of material;
a third layer of material; and
a second layer of material disposed between the first and third layer of material and wherein a thickness of the first, second and third layer is less than about 21 nm.
3. The memory device of claim 2 wherein the memory layer is formed from a metal oxide, the first layer is formed from TiO 2 , the second layer is formed from Al 2 O 3 , and the third layer is formed from TiO 2 .
4. The memory device of claim 3 wherein the first layer has a first thickness of about 17 nm and is disposed on the memory layer.
5. The memory device of claim 3 wherein the third layer has a third thickness of about 17 nm and is disposed on the memory layer.
6. The memory device of claim 3 wherein the memory layer is formed from one of AlN, TaO x , HfO x or TiO x .
7. The memory device of claim 2 wherein the first layer of material and the third layer of material are of the same material.
8. The memory device of claim 7 wherein the first layer of material and the third layer of material are not of the same thickness as the second layer of material.
9. A memory device disposed in a vertical substrate stack having alternating layers of conductive layers and insulating layers, wherein the vertical stack has one more insulating layer than conductive layers and a bottom layer being an etch stop layer and the top layer being one of the insulating layers, the memory device comprising:
a plurality of vias disposed through the top layer of the vertical stack to the etch stop layer;
a memory layer disposed adjacent the conductive layers in the vias;
multiple layers of dissimilar metal oxide layers adjacent the conductive layers in the vias configured to store a value of resistance at discrete locations along the metal oxide layer;
a plurality of layers disposed adjacent the memory layer;
a lateral electrical contact to the memory layer; and
a top contact, wherein the top contact is electrically connected to the conductive layer through the plurality of layers at one of the discrete locations along the metal oxide layer.
10. The memory device of claim 9 wherein the metal oxide layer is comprised of:
one of AlN, TaO x , HfO x or TiO x or combinations thereof.
11. The memory device of claim 9 wherein the plurality of layers comprises:
a first layer of TiO 2 ;
a third layer of TiO 2 ; and
a second layer of Al 2 O 3 disposed between the first and third layer, wherein a thickness of the first, second and third layer is less than about 21 nm.
12. The memory device of claim 11 wherein the first layer has a first thickness of about 17 nm and is disposed on the memory layer.
13. The memory device of claim 11 wherein the third layer has a third thickness of about 17 nm and is disposed on the memory layer.
14. A memory device, comprising:
a vertical stack of alternating layers of conductive and insulating layers wherein a top layer and a bottom layer are insulating layers;
a plurality of vias disposed through the vertical stack from the top layer to the bottom layer;
a memory layer disposed adjacent the conductive layers in the vias;
a selector device disposed adjacent the memory layer, wherein the selector device comprises multiple layers of dissimilar metal oxides, wherein the multiple layers of dissimilar metal oxides comprises:
a first layer of TiO 2 of in between 10 nm to 20 nm thick,
a second layer of Al 2 O 3 of in between 1 nm to 5 nm thick, and
a third layer of TiO 2 of in between 1 nm to 5 nm thick wherein the thickness for each of the first layer and the third layer is greater than the thickness of the second layer;
one or more lateral electrical contacts to the memory layer is formed through the conductive layer; and
a top contact electrically connected to the one or more lateral electrical contacts through a portion of the memory layer and the portion of the memory layer is configured to store data therein.