IP Library Granted Patent US 9,812,489
Granted Patent B2
US 9,812,489 · App. 15/133,129 · Granted Nov 7, 2017

Pixels with photodiodes formed from epitaxial silicon

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Quick Facts
Patent No.
US 9,812,489
App. No.
15/133,129
Granted
Nov 7, 2017
Kind
B2
Abstract

An image sensor may include a plurality of pixels that each contain a photodiode. The pixels may include deep photodiodes for near infrared applications. The photodiodes may be formed by growing doped epitaxial silicon in trenches formed in a substrate. The doped epitaxial silicon may be doped with phosphorus or arsenic. The pixel may include additional n-wells formed by implanting ions in the substrate. Isolation regions formed by implanting boron ions may isolate the n-wells and doped epitaxial silicon. The doped epitaxial silicon may be formed at temperatures between 500° C. and 550° C. After forming the doped epitaxial silicon, laser annealing may be used to activate the ions. Chemical mechanical planarization may also be performed to ensure that the doped epitaxial silicon has a flat and planar surface for subsequent processing.

Claims (32)

1. A method of forming a pixel comprising:

forming a trench in a substrate, wherein the substrate comprises a p-type doped substrate;

growing n-type doped epitaxial silicon in the trench;

after growing the n-type doped epitaxial silicon in the trench, growing p-type doped epitaxial silicon on the n-type doped epitaxial silicon;

forming an n-well region that overlaps the n-type doped epitaxial silicon, wherein forming the n-well region comprises implanting an n-type dopant in the p-type doped epitaxial silicon; and

forming first and second isolation regions, wherein the n-well region and the n-type doped epitaxial silicon are interposed between the first and second isolation regions.

2. The method defined in claim 1 , wherein forming the trench in the substrate comprises etching the substrate to form the trench.

3. The method defined in claim 1 , wherein the p-type doped substrate is a graded substrate with a first region and a second region, wherein the first region has a first p-type doping concentration, and wherein the second region has a second p-type doping concentration that is different than the first p-type doping concentration.

4. The method defined in claim 1 , wherein forming the first and second isolation regions comprises implanting a p-type dopant into the substrate.

5. The method defined in claim 1 , further comprising:

after growing the n-type doped epitaxial silicon in the trench, laser annealing the n-type doped epitaxial silicon.

6. The method defined in claim 5 , further comprising:

after laser annealing the n-type doped epitaxial silicon, performing chemical mechanical planarization on the n-type doped epitaxial silicon.

7. The method defined in claim 1 , wherein growing the n-type doped epitaxial silicon in the trench comprises growing the n-type doped epitaxial silicon at temperatures between 450° C. and 600° C.

8. The method defined in claim 1 , further comprising:

performing back end of line processing to form a dielectric stack and metal interconnect routing paths.

9. A method of forming a pixel comprising:

forming a gate oxide layer and a gate polysilicon layer on a substrate;

forming a first n-well in the substrate;

forming first and second isolation regions in the substrate, wherein the first n-well is interposed between the first and second isolation regions;

forming a dielectric stack and metal interconnect routing paths over the gate polysilicon layer;

after forming the dielectric stack and the metal interconnect routing paths over the gate polysilicon layer, thinning the substrate to a thickness;

after thinning the substrate to the thickness, forming a trench above the first n-well; and

growing n-type doped epitaxial silicon in the trench.

10. The method defined in claim 9 , wherein forming the first n-well in the substrate comprises implanting phosphorus into the substrate.

11. The method defined in claim 10 , further comprising:

before forming the dielectric stack and the metal interconnect routing paths over the gate polysilicon layer, forming a second n-well in the substrate.

12. The method defined in claim 11 , wherein forming the second n-well in the substrate comprises implanting arsenic into the substrate.

13. The method defined in claim 12 , wherein the n-type doped epitaxial silicon is doped with a dopant selected from the group consisting of: phosphorus and arsenic.

14. The method defined in claim 9 , further comprising:

after growing the n-type doped epitaxial silicon in the trench, laser annealing the n-type doped epitaxial silicon in the trench; and

after laser annealing the n-type doped epitaxial silicon in the trench, performing chemical mechanical planarization on the n-type doped epitaxial silicon.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 041187, FRAME 0295 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064151/0203 →
SECURITY INTEREST Recorded Dec 23, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 041187/0295 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2016
From: TEKLEAB, DANIEL
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038324/0018 →