Insulated gate switching element

1. An insulated gate switching element comprising:

a semiconductor substrate including

a first semiconductor region exposed at a surface of the semiconductor substrate, the first semiconductor region being a first conduction type,

a base region exposed at the surface of the semiconductor substrate, the base region contacting the first semiconductor region, and the base region being a second conduction type and

a second semiconductor region which is exposed at the surface of the semiconductor substrate, the second semiconductor region contacting with the base region, the second semiconductor region separated from the first semiconductor region, and the second semiconductor region being the first conduction type;

a gate insulating film disposed on the surface of the semiconductor substrate; and

a gate electrode disposed on the gate insulating film, wherein

the gate electrode faces the base region in an area the first semiconductor region and the second semiconductor region are separated from each other, the gate insulating film interposed between the gate electrode and the base region, and

a high-resistance region is disposed in at least one of a first interface and a second interface, the high-resistance region separated from the gate insulating film, the high-resistance region having higher resistance to a majority carrier of a first conduction type semiconductor than that of the base region, the first interface being an interface between the base region and the first semiconductor region, and the second interface being an interface between the base region and the second semiconductor region.

2. The insulated gate switching element according to claim 1 , wherein

the insulated gate switching element has a MOSFET structure.

3. The insulated gate switching element according to claim 1 , further comprising:

a first electrode disposed on the surface of the semiconductor substrate and connected to the first semiconductor region; and

a second electrode disposed on the surface of the semiconductor substrate and connected to the second semiconductor region, wherein

at least a portion of the high-resistance region is disposed between the first electrode and the second electrode in a plan view of the surface of the semiconductor substrate.

4. The insulated gate switching element according to claim 1 , wherein

the high-resistance region is an insulator.

5. The insulated gate switching element according to claim 1 , wherein

the high-resistance region is disposed in an entirety of the second interface excluding a position in a vicinity of the gate insulating film.

6. The insulated gate switching element according to claim 4 , wherein

a plurality of high-resistance regions are disposed at the second interface with intervals between each of the high-resistance regions.

7. The insulated gate switching element according to claim 6 , wherein

the second semiconductor region includes a high-concentration region which contacts the high-resistance region and has a higher first conduction type impurity concentration than that of the second semiconductor region in a periphery of the high-concentration region.

8. The insulated gate switching element according to claim 1 , wherein

the high-resistance region is the second conduction type, and has a higher second conduction type impurity concentration than that of the base region.

9. The insulated gate switching element according to claim 1 , wherein

the high-resistance region includes a plurality of insulators and a second conduction type region having a higher second conduction type impurity concentration than that of the base region,

the plurality of insulators are disposed at the second interface with intervals therebetween, and

the second conduction type region is disposed in the intervals between the plurality of insulators.

10. The insulated gate switching element according to claim 1 , wherein

the high-resistance region is disposed at the first interface.