Semiconductor device having a filling conductor comprising a plug portion and a cap portion and manufacturing method thereof
A semiconductor device includes a semiconductor substrate and at least one gate stack. The gate stack is present on the semiconductor substrate, and the gate stack includes at least one work function conductor and a filling conductor. The work function conductor has a recess therein. The filling conductor includes a plug portion and a cap portion. The plug portion is present in the recess of the work function conductor. The cap portion caps the work function conductor.
1. A semiconductor device, comprising:
a semiconductor substrate;
at least one gate stack present on the semiconductor substrate, the gate stack comprising:
at least one work function conductor having a tapered surface and a recess therein;
a filling conductor comprising a plug portion and a cap portion, the plug portion present in the recess of the work function conductor, the cap portion capping the work function conductor; and
a dielectric cap overlying the cap portion; and
a first gate spacer disposed on a first side of the gate stack and a second gate spacer disposed on a second side of the gate stack opposite the first side, wherein:
the dielectric cap extends between the first gate spacer and the second gate spacer, and
a sidewall of the cap portion is in direct contact with a sidewall of the first gate spacer.
2. The semiconductor device of claim 1 , wherein the filling conductor comprises tungsten.
3. The semiconductor device of claim 1 , wherein the cap portion has a width greater than that of the plug portion.
4. The semiconductor device of claim 1 , wherein the cap portion has a width not less than that of the work function conductor.
5. The semiconductor device of claim 1 , wherein the cap portion has a width not less than that of the dielectric cap.
6. The semiconductor device of claim 1 , wherein a top surface of the first gate spacer, a top surface of the second gate spacer, and a top surface of the dielectric cap are co-planar.
7. The semiconductor device of claim 1 , wherein:
the plug portion comprises a tapering plug and a bottom plug,
the tapering plug is present between the cap portion and the bottom plug, and
the tapering plug tapers from the cap portion to the bottom plug.
8. The semiconductor device of claim 1 , wherein:
the recess of the work function conductor comprises a tapering opening defined by the tapered surface and a bottom recess,
the tapering opening is present between the cap portion and the bottom recess, and
the tapering opening tapers toward the bottom recess.
9. The semiconductor device of claim 1 , wherein a sidewall of the work function conductor is in direct contact with the sidewall of the first gate spacer.
10. The semiconductor device of claim 1 , wherein a sidewall of the dielectric cap is in direct contact with the sidewall of the first gate spacer.
11. A method of manufacturing a semiconductor device, the method comprising:
forming at least two gate spacers on a semiconductor substrate;
forming at least one work function conductor between the gate spacers, the work function conductor having a recess therein;
forming a mask to conceal some of the work function conductor, wherein a portion of the work function conductor is not concealed by the mask;
recessing the work function conductor between the gate spacers to expose at least portions of sidewalls of the gate spacers, wherein the recessing comprises tapering some of the portion of the work function conductor not concealed by the mask;
removing the mask after the recessing the work function conductor; and
forming a filling conductor in the recess and in a space between the portions of the sidewalls of the gate spacers; and
forming a dielectric cap in a space between the portions of the sidewalls of the gate spacers.
12. The method of claim 11 , wherein the forming the filling conductor comprises:
overfilling the recess with the filling conductor such that the filling conductor reaches the portions of the sidewalls of the gate spacers exposed after the recessing the work function conductor.
13. The method of claim 11 , further comprising:
recessing a portion of the filling conductor in the space between the portions of the sidewalls of the gate spacers exposed after the recessing the work function conductor to define a second recess, wherein the forming the dielectric cap comprises forming the dielectric cap in the second recess over the filling conductor.
14. The method of claim 11 , further comprising:
etching the semiconductor substrate after the forming the gate spacers to define a second recess adjacent a first gate spacer of the gate spacers; and
growing an epitaxial structure in the second recess.
15. The method of claim 11 , wherein the work function conductor directly contacts sidewalls of the gate spacers.
16. The method of claim 11 , wherein the forming the mask comprises:
depositing the mask; and
removing a portion of the mask to expose the portion of the work function conductor prior to the recessing the work function conductor.
17. A semiconductor device, comprising:
a semiconductor substrate;
a first gate spacer and a second gate spacer; and
at least one gate stack present on the semiconductor substrate and disposed between the first gate spacer and the second gate spacer, the gate stack comprising:
a gate dielectric in direct contact with a sidewall of the first gate spacer and a sidewall of the second gate spacer;
a first work function conductor over the gate dielectric and in direct contact with the sidewall of the first gate spacer and the sidewall of the second gate spacer, wherein the first work function conductor have a tapered surface and defines a recess;
a filling conductor comprising a plug portion and a cap portion, wherein:
the plug portion is present in the recess of the first work function conductor, and
the cap portion caps the first work function conductor; and
a dielectric cap overlying the cap portion and between the first gate spacer and the second gate spacer.
18. The semiconductor device of claim 17 , wherein the cap portion is in direct contact with the sidewall of the first gate spacer and the sidewall of the second gate spacer.
19. The semiconductor device of claim 17 , wherein the dielectric cap is in direct contact with the sidewall of the first gate spacer and the sidewall of the second gate spacer.
20. The semiconductor device of claim 17 , wherein the gate stack further comprises:
a second work function conductor present in the recess of the first work function conductor and disposed between the plug portion and the first work function conductor.