Pixels with high dynamic range and a global shutter scanning mode
A CMOS image sensor may have back-side illuminated pixels and operate in a global shutter scanning mode. The CMOS image sensor may be implemented using three-layer chip stacking. The chip to chip electrical connections between the upper chip and the middle chip may be formed via hybrid bonding. Two bonding pads may be included in each pixel. The electrical connections between the middle chip and the lower chip may be formed at the periphery of the array. Using three-layer chip stacking with hybrid bonding allows for the transferring and storing of signals from the upper chip on the middle chip. A signal from low light level illumination and a charge overflow signal from high light level illumination may both be transferred to the middle chip. The image sensor may be able to use a global shutter scanning mode having high dynamic range.
1. An image sensor that includes an imaging pixel, wherein the imaging pixel comprises:
a first substrate;
a second substrate;
a photodiode formed in the first substrate;
first and second charge transfer gates formed in the first substrate;
first and second charge storage regions formed in the second substrate; and
first and second interconnect layers, wherein the first interconnect layer couples the first charge transfer gate to the first charge storage region, and wherein the second interconnect layer couples the second charge transfer gate to the second charge storage region.
2. The image sensor defined in claim 1 , wherein the second gate comprises a charge overflow gate, and wherein the charge overflow gate comprises a buried channel transistor with ion implantations formed under the charge overflow gate.
3. The image sensor defined in claim 2 , wherein the image sensor is configured to operate in a global shutter scanning mode.
4. The image sensor defined in claim 1 , wherein the photodiode is configured to generate a total amount of charge in response to incident light, wherein the imaging pixel is configured to transfer a first amount of the total amount of charge to the first charge storage region using the first charge transfer gate, and wherein the first charge storage region is a floating diffusion node.
5. The image sensor defined in claim 4 , wherein the imaging pixel is configured to transfer a second amount of the total amount of charge to the second charge storage region using the second charge transfer gate, wherein the second charge storage region comprises a charge storage capacitor.
6. The image sensor defined in claim 5 , wherein the first and second interconnect layers are formed on opposing sides of the imaging pixel.
7. The image sensor defined in claim 5 , further comprising isolation regions that surround the imaging pixel, wherein the isolation regions comprise doped silicon.
8. The image sensor defined in claim 5 , further comprising:
a reset transistor configured to reset the charge storage capacitor to a bias voltage; and
a source follower transistor coupled to the charge storage capacitor.
9. The image sensor defined in claim 5 , further comprising:
a source follower transistor coupled to the floating diffusion node, wherein the source follower transistor is formed in the second substrate.
10. The image sensor defined in claim 5 , further comprising:
a double reset circuit formed in the second substrate that is configured to reset the floating diffusion node.
11. The image sensor defined in claim 10 , further comprising:
a third substrate; and
a column feedback amplifier formed in the third substrate, wherein the column feedback amplifier is coupled to the double reset circuit by a third interconnect layer.
12. The image sensor defined in claim 5 , further comprising:
an active reset circuit formed in the second substrate that is configured to reset the floating diffusion node.
13. The image sensor defined in claim 5 , further comprising:
a third substrate; and
a correlated double sampling signal processing circuit in the third substrate.
14. An imaging pixel comprising:
a photodiode;
a floating diffusion node;
a charge storage capacitor;
a first charge transfer transistor that is coupled between the photodiode and the floating diffusion node;
a second charge transfer transistor that is coupled between the photodiode and the charge storage capacitor; and
an active reset circuit coupled to the floating diffusion node.
15. The imaging pixel defined in claim 14 , further comprising:
a first source follower transistor coupled to the floating diffusion node; and
a second source follower transistor coupled to the charge storage capacitor.
16. The imaging pixel defined in claim 14 , wherein the active reset circuit comprises:
a reset transistor coupled to the floating diffusion node;
a p-channel gain transistor; and
an n-channel load transistor.
17. The imaging pixel defined in claim 14 , wherein the active reset circuit comprises:
a reset transistor coupled to the floating diffusion node;
an n-channel gain transistor; and
a p-channel load transistor.
18. The imaging pixel defined in claim 14 , wherein the second charge transfer transistor is a buried channel transistor with ion implantations formed under a charge overflow gate.
19. An imaging pixel comprising:
a photodiode formed in a first substrate;
a floating diffusion node formed in a second substrate;
a charge storage capacitor formed in the second substrate;
a first charge transfer gate that is coupled between the photodiode and the floating diffusion node, wherein the first charge transfer gate is formed in the first substrate;
a second charge transfer gate that is coupled between the photodiode and the charge storage capacitor, wherein the second charge transfer gate is formed in the first substrate; and
an active reset circuit coupled to the floating diffusion node, wherein the active reset circuit comprises a gain transistor, a load transistor, and a reset transistor, and wherein the reset transistor is coupled to the floating diffusion node.
20. The imaging pixel defined in claim 19 , wherein the gain transistor has a first polarity, wherein the load transistor has a second polarity, and wherein the first and second polarities are different.