Dual-rail power equalizer
A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.
1. A processing device comprising:
a memory cell array coupled to a first power rail through a first switch to receive a first voltage level;
logic circuitry coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level;
a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry, wherein the power switch has a first end coupled to the memory cell array and a second end coupled to the second power rail, and is operative to be enabled to supply the second voltage level to both the memory cell array and the logic circuitry.
2. The processing device of claim 1 , wherein when the power switch is disabled, the first switch is operative to be enabled to supply the first voltage level to the memory cell array.
3. The processing device of claim 1 , wherein the power switch is operative to be turned on and off according to a value stored in a designated register.
4. A processing device comprising:
a memory cell array coupled to a first power rail through a first switch to receive a first voltage level;
logic circuitry coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level;
a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry, wherein the memory cell array and the logic circuitry operate at two different voltage levels with the power switch disabled when the second voltage level is below a threshold.
5. The processing device of claim 4 , wherein when the second voltage level exceeds the threshold, the memory cell array and the logic unit operate at the equalized voltage level with the power switch enabled.
6. The processing device of claim 4 , wherein the power switch is operative to be turned on and off according to a value stored in a designated register.
7. A processing device comprising:
a memory cell array coupled to a first power rail through a first switch to receive a first voltage level;
logic circuitry coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level;
a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry, wherein the power switch is a P-type Field-Effect Transistor (FET).
8. The processing device of claim 7 , wherein the power switch is operative to be turned on and off according to a value stored in a designated register.
9. The processing device of claim 7 , wherein the power switch has a first end coupled to the memory cell array and a second end coupled to the second power rail, and is operative to be enabled to supply the second voltage level to both the memory cell array and the logic circuitry.
10. The processing device of claim 9 , wherein when the power switch is disabled, the first switch is operative to be enabled to supply the first voltage level to the memory cell array.
11. The processing device of claim 7 , wherein the memory cell array and the logic circuitry operate at two different voltage levels with the power switch disabled when the second voltage level is below a threshold.
12. The processing device of claim 11 , wherein when the second voltage level exceeds the threshold, the memory cell array and the logic unit operate at the equalized voltage level with the power switch enabled.
13. A method of a processing device that includes a memory cell array and logic circuitry, comprising:
disabling a power switch for the memory cell array to receive a first voltage level supplied by a first power rail and for the logic circuitry to receive a second voltage level supplied by a second power rail, wherein the first voltage level is different from the second voltage level;
enabling the power switch to equalize voltage supplied to the memory cell array and the logic circuitry; and
disabling the power switch when the second voltage level is below a threshold.
14. The method of claim 13 , further comprising:
enabling the power switch when the second voltage level exceeds a threshold.
15. The method of claim 13 , wherein the power switch has a first end coupled to the memory cell array and a second end coupled to the second power rail, and wherein enabling the power switch further comprises: supplying the second voltage level to both the memory cell array and the logic circuitry.
16. The method of claim 13 , further comprising: generating a value in a designated register to enable or disable the power switch.