Glitch-free clock switching circuit using Muller C-elements

1. A clock switching circuit, comprising:

first and second clock lines that provide first and second clock signals;

first and second selection lines that provide first and second selection signals;

a first Muller C-element connected at its inputs to the first clock line and the first selection line;

a second Muller C-element connected at its inputs to the first selection line and an output of a first logic gate;

a third Muller C-element connected at its inputs to the second selection line and the second clock line;

a fourth Muller C-element connected at its inputs to the second selection line and an output of a second logic gate;

a first delay cell connected at its inputs to the first clock line and an output of the second Muller C-element;

a second delay cell connected at its inputs to an output of the fourth Muller C-element and the second clock line;

a first AND gate connected at its inputs to the first clock line, an output of the first Muller C-element, and an output of the first delay cell;

a second AND gate connected at its inputs to an output of the second delay cell, an output of the third Muller C-element, and the second clock line; and

an OR gate connected at its inputs to outputs of the first and second AND gates and providing an output clock signal at its output, wherein the first selection signal is used to select the first clock signal as the output clock signal and the second selection signal is used to select the second clock signal as the output clock signal.

2. The clock switching circuit of claim 1 , wherein:

the first logic gate is an AND gate connected at one input to the first selection line and receives at another input an inverted value of the output of the OR gate, and

the second logic gate is an AND gate connected at one input to the second selection line and receives at another input the inverted value of the output of the OR gate.

3. The clock switching circuit of claim 2 , further comprising:

a third clock line providing a third clock signal;

a third selection line providing a third selection signal that is used to select the third clock signal as the output clock signal;

a fifth Muller C-element connected at its inputs to the third clock line and the third selection line;

a sixth Muller C-element connected at its inputs to the third selection line and an output of a third logic gate, the third logic gate being an AND gate connected at one input to the third selection line and receiving at another input the inverted value of the output of the OR gate;

a third delay cell connected at its inputs to the third clock line and an output of the sixth Muller C-element; and

a third AND gate connected at its inputs to the third clock line, an output of the fifth Muller C-element, and an output of the third delay cell, the third AND gate having an output connected to an input of the OR gate.

4. The clock switching circuit of claim 1 , wherein the first delay cell includes:

a first delay Muller C-element connected at its inputs to the output of the second Muller C-element and the first clock line, and

a first delay inverter connected at its input to the first clock line, and

the second delay cell includes:

a second delay Muller C-element connected at its inputs to the output of the fourth Muller C-element and the second clock line, and

a second delay inverter connected at its input to the second clock line.

5. The clock switching circuit of claim 4 , wherein:

the first delay cell further includes a third delay Muller C-element connected at its inputs to an output of the first delay Muller C-element and an output of the first delay inverter, and

the second delay cell further includes a fourth delay Muller C-element connected at its inputs to an output of the second delay Muller C-element and an output of the second delay inverter.

6. The clock switching circuit of claim 1 , wherein:

the first logic gate is a NOR gate connected at its inputs to the second selection line and the second clock line, and

the second logic gate is a NOR gate connected at its inputs to the first selection line and the first clock line.

7. The clock switching circuit of claim 1 , wherein the second selection line is connected to an output of an inverter, the inverter being connected at its input to the first selection line.

8. A clock switching circuit, comprising:

a plurality of clock lines, each providing a respective clock signal;

an OR gate providing an output clock signal;

a plurality of selection lines, each corresponding to a respective one of the plurality of clock lines and providing a selection signal used for selecting a corresponding clock signal as the output clock signal; and

a plurality of clock selection modules, each of which includes:

a first Muller C-element having its inputs connected to a corresponding clock line and corresponding selection line,

a second Muller C-element having its inputs connected to the corresponding selection line and an output of a first AND gate, the first AND gate having one input connected to the corresponding selection line and receiving at another input an inverted value of the output of the OR gate,

a delay cell having its inputs connected to the corresponding clock line and an output of the second Muller C-element, and

a second AND gate having its inputs connected to the corresponding clock line, an output of the first Muller C-element, and an output of the delay cell, an output of the second AND gate being connected to an input of the OR gate.

9. The clock switching circuit of claim 8 , wherein each delay cell includes:

a first delay Muller C-element connected at its inputs to the output of the second Muller C-element and the corresponding clock line, and

a first delay inverter connected at its input to the corresponding clock line.

10. The clock switching circuit of claim 9 , wherein each delay cell further includes a second delay Muller C-element connected at its inputs to an output of the first delay Muller C-element and an output of the first delay inverter.