Semiconductor device and trench field plate field effect transistor with a field dielectric including thermally grown and deposited portions

1. A semiconductor device comprising:

compensation structures extending from a first surface into a semiconductor portion, wherein sections of the semiconductor portion between neighboring ones of the compensation structures form semiconductor mesas; and

a field electrode in the compensation structures, wherein a field dielectric separating the field electrode from the semiconductor portion comprises a thermally grown portion, which directly adjoins the semiconductor portion, and a not fully densified deposited portion with a lower density than the thermally grown portion.

2. The semiconductor device of claim 1 , wherein

the thermally grown portion is thermal silicon oxide.

3. The semiconductor device of claim 1 , wherein

the not fully densified deposited portion is a silicon oxide based on a deposition process using tetraethyl orthosilicate as precursor material.

4. The semiconductor device of claim 1 , wherein

the not fully densified deposited portion has a lower density than after an anneal at 1100° Celsius for 30 minutes.

5. The semiconductor device of claim 1 , wherein

the not fully densified deposited portion has a density equal to or lower than after an anneal at 1050° Celsius for 30 minutes.

6. The semiconductor device of claim 1 , wherein

in an etch solution containing a mixture of 33 wt. % ammonium fluoride NH 4 F and 4.15 wt. % hydrofluoric acid, an etch selectivity between the not fully densified deposited portion and the thermally grown portion is between (2:1) and (4:1).

7. The semiconductor device of claim 1 , wherein

in an etch solution containing an mixture of 33 wt. % ammonium fluoride NH 4 F and 4.15 wt. % hydrofluoric acid, an etch selectivity between the not fully densified deposited portion and a fully densified deposited silicon oxide based on tetraethyl orthosilicate as precursor material is between (2:1) and (4:1).

8. The semiconductor device of claim 1 , wherein

a direction of mechanical stress induced into the semiconductor portion by the not fully densified deposited portion is opposite to a direction of mechanical stress induced into the semiconductor portion by the thermally grown portion.

9. The semiconductor device of claim 1 , wherein

a ratio of a mean thickness of the thermally grown portion to a mean thickness of the not fully densified deposited portion is at least 1:1 and at most 9:1.

10. The semiconductor device of claim 1 , further comprising

a gate structure comprising a gate electrode, wherein a gate dielectric separates the gate electrode from the semiconductor mesas and wherein first mesa sections of the semiconductor mesas separate the gate structure from the compensation structures.

11. The semiconductor device of claim 1 , further comprising

a gate electrode in the compensation structures, wherein a gate dielectric separates the gate electrode from the semiconductor mesas and an intermediate dielectric separates the gate electrode and the field electrode.

12. The semiconductor device of claim 11 , wherein

a width of the gate electrode corresponds to a width of the thermally grown portion.

13. The semiconductor device of claim 11 , wherein

the intermediate dielectric separates the gate and field electrodes along a direction parallel to the first surface and in each compensation structure two segments of the gate electrode are formed on opposite sides of an intermediate field electrode.

14. The semiconductor device of claim 11 , wherein

the gate dielectric comprises a thermal portion, which directly adjoins the semiconductor portion, and a not fully densified non-thermal portion having a lower density than the thermally grown portion.

15. The semiconductor device of claim 1 , wherein

the compensation structures are parallel stripes extending in a direction parallel to the first surface.

16. The semiconductor device of claim 1 , wherein

the compensation structures are arranged in lines extending in a direction parallel to the first surface and each line comprises a plurality of the compensation structures.

17. The semiconductor device of claim 1 , further comprising:

a first load electrode and an interlayer dielectric directly adjoining the first surface and separating the first load electrode and the semiconductor portion, and

trench field plate contact structures extending through the interlayer dielectric and between two segments of the gate electrode of the same compensation structure and electrically connecting the first load electrode with the field electrode.

18. The semiconductor device of claim 1 , wherein

the first load electrode is electrically connected with the field electrode.

19. The semiconductor device of claim 1 , further comprising:

a drift zone formed in the semiconductor portion, wherein the drift zone forms first pn junctions with body zones formed in the semiconductor mesas and the body zones form second pn junctions with source zones in the semiconductor mesas.

20. The semiconductor device of claim 19 , further comprising:

a field stop zone formed in the semiconductor portion, wherein the field stop zone and the drift zone formed a unipolar homojunction and a mean net dopant concentration in the field stop zone is at least two times as high as in the drift zone.

21. The semiconductor device of claim 19 , wherein

the drift zone contains metallic recombination centers.

22. A trench field plate field effect transistor comprising:

compensation structures extending from a first surface into a semiconductor portion, wherein sections of the semiconductor portion between neighboring ones of the compensation structures form semiconductor mesas; and

a field electrode in the compensation structures, wherein a field dielectric separating the field electrode from the semiconductor portion comprises a thermally grown portion, which directly adjoins the semiconductor portion, and a not fully densified deposited portion having a lower density than the thermally grown portion.