System and method of executing a plurality of threads using thread switching on execution time-out using instruction re-write
A system includes circuitry configured to execute a first thread of a plurality of threads, measure an execution time period during which the circuitry executes the first thread without executing other threads of the plurality of threads, determine whether the measured execution time period exceeds a threshold value, specify first address information of a first instruction which is included in the first thread when it is determined that the measured execution time period exceeds the threshold value, the first instruction being an instruction that is scheduled to be executed, exchange the first instruction stored in an address region specified by the first address information with a second instruction instructing the circuitry to switch from executing the first thread to executing a second thread of the plurality of threads, and switch from executing the first thread to the executing the second thread by executing the second instruction.
1. A system configured to execute a plurality of threads included in a computer program, the system comprising:
a memory; and
a hardware processor coupled to the memory and configured to
detect a first thread to be switched from among the plurality of threads based on an execution status for each of the plurality of threads,
acquire a function called in the first thread by referring to active function information that includes functions called most recently in an active thread,
acquire first addresses of all of branch instructions included in the called function,
rewrite each of the branch instructions stored in a storage area of the memory corresponding to the acquired first addresses into a call instruction for executing a switching process for switching from the first thread to a second thread of the plurality of threads, and
switch from executing the first thread to executing the second thread by executing the call instruction.
2. The system according to claim 1 , wherein
the execution status indicates an elapsed time since a core of the hardware processor has been dispatched to a thread of the plurality of threads.
3. The system according to claim 2 , wherein the hardware processor is further configured to
obtain second addresses of the branch instructions included in the called function during the compilation of the computer program, and
specify the first addresses by referring to the second address.
4. The system according to claim 3 , wherein
the hardware processor is further configured to obtain a third address of a branch instruction among the branch instructions included in the called function.
5. The system according to claim 4 , wherein the hardware processor is further configured to
specify the third address of a branch instruction executed most recently, and
specify each of the branch instructions based on the third address.
6. The system according to claim 4 , wherein
the hardware processor is further configured to specify the third address of the branch instruction using a Last Branch Record functionality and a Precise Event Based Sampling functionality.
7. The system according to claim 1 , wherein
the hardware processor is further configured to function as a scheduler configured to switch the first thread, and
the call instruction is an instruction for calling the scheduler.
8. A method of executing a plurality of threads included in a computer program by a hardware processor, the method comprising:
detecting a first thread to be switched from among the plurality of threads based on an execution status for each of the plurality of threads;
acquiring a function called in the first thread by referring to active function information that includes functions called most recently in an active thread;
acquiring first addresses of all of branch instructions included in the called function;
rewriting each of the branch instructions stored in a storage area of the memory corresponding to the acquired first addresses into a call instruction for executing a switching process for switching from the first thread to a second thread of the plurality of threads; and
switching from executing the first thread to the executing the second thread by executing the call instruction.
9. The method according to claim 8 ,
wherein the execution status indicates an elapsed time since a core of the hardware processor has been dispatched to a thread of the plurality of threads.
10. The method according to claim 9 , further comprising
obtaining second addresses of the branch instructions included in the called function during the compilation of the computer program, and
specifying the first addresses by referring to the second address.
11. The method according to claim 10 , further comprising:
obtaining a third address of a branch instruction among the branch instructions included in the called function.
12. The method according to claim 11 , wherein
the obtaining the third address includes specifying a most recently executed branch instruction, and
the method further comprising
specifying each of the branch instructions by referring to the third address.
13. The method according to claim 11 , wherein
the obtaining the third address of the branch instruction is executed by using a Last Branch Record functionality and a Precise Event Based Sampling functionality.
14. One or more non-transitory computer-readable medium configured to store computer program instructions, which when executed by a system including a hardware processor, cause the system to:
detect a first thread to be switched from among the plurality of threads based on an execution status for each of the plurality of threads,
acquire a function called in the first thread by referring to active function information that includes functions called most recently in an active thread,
acquire first addresses of all of branch instructions included in the called function,
rewrite each of the branch instructions stored in a storage area of the memory corresponding to the acquired first addresses into a call instruction for executing a switching process for switching from the first thread to a second thread of the plurality of threads, and
switch from executing the first thread to the executing the second thread by executing the call instruction.
15. The one or more non-transitory computer-readable medium according to claim 14 ,
wherein the execution status indicates an elapsed time since a core of the hardware processor has been dispatched to a thread of the plurality of threads.
16. The one or more non-transitory computer-readable medium according to claim 15 , wherein the computer program instructions further cause the system to:
obtain second addresses of the branch instructions included in the called function during the compilation of the computer program, and
specify the first addresses by referring to the second address.
17. The one or more non-transitory computer-readable medium according to claim 16 , wherein the computer program instructions further cause the system to:
obtain a third address of a branch instruction among the plurality of branch instructions included in the called function.