IP Library › Granted Patent US 10,185,449
Granted Patent B2
US 10,185,449 · App. 15/140,626 · Granted Jan 22, 2019

Touch panel

Inventors: Hideaki Shishido (Atsugi, JP); Yoshiharu Hirakata (Ebina, JP); Daisuke Kubota (Atsugi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G06F3/044G02F1/13338G06F3/0412G06F3/0416G09G3/00G06F2203/04102G06F2203/04103G06F2203/04107G06F2203/04111G06F2203/04112
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Quick Facts
Patent No.
US 10,185,449
App. No.
15/140,626
Granted
Jan 22, 2019
Kind
B2
Abstract

To provide a thin touch panel, a touch panel with high visibility, a lightweight touch panel, or a touch panel with low power consumption. A pair of conductive layers is included in a capacitive touch sensor. The two conductive layers have a mesh shape including a plurality of openings. Furthermore, the conductive layers are provided to overlap with a region between two display elements in a plan view. Furthermore, the conductive layers included in the touch sensor are provided between two substrates included in the touch panel, and a conductive layer capable of supplying a constant potential is provided between a circuit which drives a display element and the pair of conductive layers.

Claims (118)

1. A touch panel comprising:

a first substrate;

a first conductive layer;

a second conductive layer;

a third conductive layer;

a fourth conductive layer; and

a liquid crystal layer,

wherein the third conductive layer is over the first substrate,

wherein the fourth conductive layer is apart from the third conductive layer on a same plane,

wherein the liquid crystal layer is above the third conductive layer,

wherein the second conductive layer is above the liquid crystal layer,

wherein the first conductive layer is above the second conductive layer,

wherein the first conductive layer has a mesh shape comprising a plurality of openings,

wherein the second conductive layer is configured to transmit visible light and comprises a portion overlapping with the third conductive layer and a portion overlapping with the fourth conductive layer,

wherein the third conductive layer and the fourth conductive layer are configured to transmit visible light,

wherein the third conductive layer comprises a portion overlapping with one of the plurality of openings,

wherein the fourth conductive layer comprises a portion overlapping with another one of the plurality of openings, and

wherein the first conductive layer is between the third conductive layer and the fourth conductive layer in a plan view.

2. The touch panel according to claim 1 ,

wherein the second conductive layer serves as a common electrode, and

wherein the third conductive layer and the fourth conductive layer each serve as a pixel electrode.

3. The touch panel according to claim 1 , wherein the second conductive layer is electrically connected to a terminal supplied with a constant potential.

4. The touch panel according to claim 1 ,

wherein a second substrate is above the first conductive layer, and

wherein the first conductive layer and the second conductive layer are formed over the second substrate.

5. The touch panel according to claim 1 ,

wherein a light-blocking layer is above the first conductive layer, and

wherein the light-blocking layer and the first conductive layer overlap with each other in a region.

6. The touch panel according to claim 1 , wherein a circularly polarizing plate is above the first conductive layer.

7. The touch panel according to claim 1 ,

wherein a first coloring layer and a second coloring layer are above the third conductive layer,

wherein the first coloring layer comprises a region overlapping with the one of the plurality of openings, and

wherein the second coloring layer comprises a region overlapping with another one of the plurality of openings.

8. The touch panel according to claim 7 , wherein the first conductive layer comprises a portion overlapping with at least one of the first coloring layer and the second coloring layer.

9. The touch panel according to claim 8 ,

wherein the transistor comprises a first gate electrode and a second gate electrode,

wherein the first gate electrode is below the semiconductor layer,

wherein the second gate electrode is above the semiconductor layer, and

wherein the second gate electrode, the semiconductor layer, and the third conductive layer overlap with each other in a region.

10. The touch panel according to claim 8 ,

wherein the transistor comprises a first gate electrode and a second gate electrode,

wherein the first gate electrode is below the semiconductor layer,

wherein the second gate electrode is above the semiconductor layer, and

wherein the second gate electrode, the semiconductor layer, and the third conductive layer overlap with each other in a region.

11. The touch panel according to claim 1 ,

wherein a spacer is above the third conductive layer and below the second conductive layer, and

wherein the spacer comprises a portion overlapping with the first conductive layer.

12. The touch panel according to claim 1 ,

wherein a transistor is between the liquid crystal layer and the first substrate,

wherein one of a source and a drain of the transistor is electrically connected to the third conductive layer, and

wherein the transistor comprises a semiconductor layer containing an oxide semiconductor.

13. The touch panel according to claim 12 ,

wherein the transistor comprises a first gate electrode and a second gate electrode,

wherein the first gate electrode is below the semiconductor layer,

wherein the second gate electrode is above the semiconductor layer, and

wherein the second gate electrode, the semiconductor layer, and the third conductive layer overlap with each other in a region.

14. The touch panel according to claim 13 , wherein the second gate electrode and the semiconductor layer comprise a same metal element.

15. The touch panel according to claim 1 ,

wherein a transistor is between the liquid crystal layer and the first substrate,

wherein one of a source and a drain of the transistor is electrically connected to the third conductive layer, and

wherein the transistor comprises a semiconductor layer containing amorphous silicon, polycrystalline silicon, or single crystal silicon.

16. A touch panel comprising:

a first substrate;

a first conductive layer;

a second conductive layer;

a third conductive layer;

a fourth conductive layer;

a fifth conductive layer; and

a liquid crystal layer,

wherein the fifth conductive layer is over the first substrate,

wherein the fifth conductive layer comprises a portion overlapping with the third conductive layer and a portion overlapping with the fourth conductive layer,

wherein the fourth conductive layer is apart from the third conductive layer on a same plane,

wherein the liquid crystal layer is above the third conductive layer and the fifth conductive layer,

wherein the second conductive layer is above the liquid crystal layer,

wherein the first conductive layer is above the second conductive layer,

wherein the first conductive layer has a mesh shape comprising a plurality of openings,

wherein the second conductive layer is configured to transmit visible light and comprises a portion overlapping with the third conductive layer and a portion overlapping with the fourth conductive layer,

wherein the third conductive layer comprises a portion overlapping with one of the plurality of openings,

wherein the fourth conductive layer comprises a portion overlapping with another one of the plurality of openings,

wherein the fifth conductive layer is configured to transmit visible light or the third conductive layer and the fourth conductive layer are configured to transmit visible light,

wherein the first conductive layer is between the third conductive layer and the fourth conductive layer in a plan view,

wherein the third conductive layer or the fifth conductive layer has a comb-like shape or comprises a slit,

wherein the one of the plurality of openings, the third conductive layer, and the fifth conductive layer overlap with each other in a first region, and

wherein the one of the plurality of openings overlaps with one of the third conductive layer and the fifth conductive layer and does not overlap with the other of the third conductive layer and the fifth conductive layer in a second region.

17. The touch panel according to claim 16 ,

wherein the third conductive layer and the fourth conductive layer each serve as a pixel electrode, and

wherein the fifth conductive layer serves as a common electrode.

18. The touch panel according to claim 16 , wherein the fifth conductive layer is below the third conductive layer and the fourth conductive layer.

19. The touch panel according to claim 16 , wherein the second conductive layer is electrically connected to a terminal supplied with a constant potential.

20. The touch panel according to claim 16 ,

wherein a second substrate is above the first conductive layer, and

wherein the first conductive layer and the second conductive layer are formed over the second substrate.

21. The touch panel according to claim 16 ,

wherein a light-blocking layer is above the first conductive layer, and

wherein the light-blocking layer and the first conductive layer overlap with each other in a region.

22. The touch panel according to claim 16 , wherein a circularly polarizing plate is above the first conductive layer.

23. The touch panel according to claim 16 ,

wherein a first coloring layer and a second coloring layer are above the third conductive layer,

wherein the first coloring layer comprises a region overlapping with the one of the plurality of openings, and

wherein the second coloring layer comprises a region overlapping with another one of the plurality of openings.

24. The touch panel according to claim 23 , wherein the first conductive layer comprises a portion overlapping with at least one of the first coloring layer and the second coloring layer.

25. The touch panel according to claim 16 ,

wherein a spacer is above the third conductive layer and below the second conductive layer, and

wherein the spacer comprises a portion overlapping with the first conductive layer.

26. The touch panel according to claim 16 ,

wherein a transistor is between the liquid crystal layer and the first substrate,

wherein one of a source and a drain of the transistor is electrically connected to the third conductive layer, and

wherein the transistor comprises a semiconductor layer containing an oxide semiconductor.

27. The touch panel according to claim 26 ,

wherein the transistor comprises a first gate electrode and a second gate electrode,

wherein the first gate electrode is below the semiconductor layer,

wherein the second gate electrode is above the semiconductor layer, and

wherein the second gate electrode, the semiconductor layer, and the third conductive layer overlap with each other in a region.

28. The touch panel according to claim 27 , wherein the second gate electrode and the semiconductor layer comprise a same metal element.

29. The touch panel according to claim 16 ,

wherein a transistor is between the liquid crystal layer and the first substrate,

wherein one of a source and a drain of the transistor is electrically connected to the third conductive layer, and

wherein the transistor comprises a semiconductor layer containing amorphous silicon, polycrystalline silicon, or single crystal silicon.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2016
From: SHISHIDO, HIDEAKI; HIRAKATA, YOSHIHARU; KUBOTA, DAISUKE
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 038402/0316 →
Priority Claims (2)
JP 2015-095745 · May 8, 2015 · national
JP 2015-095796 · May 8, 2015 · national
Continuity (1)
Related Publication 20160328051A1 · Nov 10, 2016
Cited By (3)
US 12,353,658 US 12,669,886 US 12,737,062