IP Library Granted Patent US 9,865,531
Granted Patent B2
US 9,865,531 · App. 15/142,588 · Granted Jan 9, 2018

Power module package having patterned insulation metal substrate

Inventors: Hsin-Chang Tsai (Taoyuan, TW); Chia-Yen Lee (Taoyuan, TW); Peng-Hsin Lee (Taoyuan, TW)
Assignee: Delta Electronics, Inc.
H01L23/49575H01L21/4825H01L21/4839H01L23/49548H01L23/49586H01L24/49H01L2224/48091H01L2924/01007H01L2924/01029H01L2924/01031H01L2924/13064
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,865,531
App. No.
15/142,588
Granted
Jan 9, 2018
Kind
B2
Abstract

A power module package is provided, including a substrate, a first chip, and a second chip. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip.

Claims (21)

1. A substrate, comprising:

a metal carrier;

a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier; and

a patterned conductive layer disposed on the patterned insulation layer;

wherein the metal carrier includes a cavity, a recess or a slot not extended through the metal carrier and not covered by the patterned insulation layer.

2. The substrate as claimed in claim 1 , wherein the metal carrier is a lead frame comprising copper.

3. The substrate as claimed in claim 1 , wherein the cavity, recess or slot is formed on the metal carrier and/or that the metal carrier includes first, second and third sections formed with a gap therebetween and connected by wire with each other and the cavity, recess or slot is formed in the second section of the metal carrier.

4. A power module package, comprising:

a substrate including a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer;

a first chip disposed on the metal carrier that includes a cavity, a recess or a slot which is not covered by the patterned insulation layer; and

a second chip disposed on the patterned conductive layer and electrically connected to the first chip.

5. The power module package as claimed in claim 4 , wherein the first chip is disposed in the cavity, the recess or the slot.

6. The power module package as claimed in claim 4 , where the patterned insulation layer includes an opening, and the first chip is disposed therein.

7. The power module package as claimed in claim 4 , wherein the patterned insulation layer includes a first patterned insulation portion covered by a part of the patterned conductive layer and a second patterned insulation portion, and the second chip is disposed on the part of the patterned conductive layer.

8. The power module package as claimed in claim 4 , wherein the patterned insulation layer includes a first patterned insulation portion covered by a part of the patterned conductive layer and a second patterned insulation portion covered by another part of the patterned conductive layer, and the first chip is electrically connected to the another part of the patterned conductive layer.

9. The power module package as claimed in claim 4 , wherein the first chip is directly connected to the metal carrier.

10. The power module package as claimed in claim 4 , wherein the metal carrier is a lead frame comprising copper.

11. The power module package as claimed in claim 4 , wherein the first chip is a lateral semiconductor component.

12. The power module package as claimed in claim 4 , wherein the second chip is a vertical semiconductor component.

13. The power module package as claimed in claim 4 , wherein the first chip has an active side with electrodes thereon and a bottom side opposite to the active side, and the first chip is disposed on the metal carrier via the bottom side.

14. The power module package as claimed in claim 4 , wherein the cavity, recess or slot is formed on the metal carrier and/or that the metal carrier includes first, second and third sections formed with a gap therebetween and connected by wire with each other and the cavity, recess or slot is formed in the second section of the metal carrier.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2022
From: DELTA ELECTRONICS, INC.
To: ANCORA SEMICONDUCTORS INC.
Reel/Frame 061695/0106 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2016
From: TSAI, HSIN-CHANG; LEE, CHIA-YEN; LEE, PENG-HSIN
To: DELTA ELECTRONICS, INC.
Reel/Frame 038435/0334 →
Continuity (1)
Related Publication 20170317014A1 · Nov 2, 2017