Temperature sensing apparatus
An apparatus for temperature sensing may include: a bias generator suitable for generating a complementary-to-absolute-temperature (CTAT) bias voltage; a regulator suitable for regulating a bias voltage by using CTAT bias voltage and outputting a regulated bias voltage; and a ring oscillator suitable for receiving the regulated bias voltage and generating an oscillation signal based on the regulated bias voltage.
1. An apparatus comprising:
a bias generator configured to generate a complementary-to-absolute-temperature (CTAT) bias voltage, the bias generator includes a current source driving a bias voltage, and a first transistor coupled with a second transistor in series between the bias voltage and a ground terminal;
a regulator configured to regulate the bias voltage by using the CTAT bias voltage and outputting a regulated bias voltage; and
a ring oscillator configured to receive the regulated bias voltage and generating an oscillation signal based on the regulated bias voltage.
2. The apparatus of claim 1 , wherein the ring oscillator includes a complementary metal oxide semiconductor (CMOS) ring oscillator having:
a cascade of inverters with odd number of stages in a ring shape, suitable for receiving the regulated bias voltage and outputting an inverted bias voltage; and
a frequency counter suitable for receiving the inverted bias voltage, and counting the inverted bias voltage according to a reference clock to generate the oscillation signal.
3. The apparatus of claim 2 , wherein the
current source includes a first terminal coupled to a power supply voltage terminal and a second terminal driving the bias voltage.
4. The apparatus of claim 1 , wherein the first transistor includes a NMOS transistor having a first terminal, a second terminal and a third terminal connected to the first terminal; and
the second transistor includes a PMOS transistor having a first terminal connected to the second terminal of the NMOS transistor, a second terminal and a third terminal connected to the ground terminal.
5. The apparatus of claim 4 , wherein the CTAT bias voltage VR 1 is substantially equal to as follows:
VR 1≈ VTp+VTn
where VTp and VTn are the threshold voltages for the PMOS transistor MP 1 and the NMOS transistor MN 1 , respectively.
6. The apparatus of claim 4 , wherein the regulator includes:
an operational amplifier including a first input terminal for receiving the bias voltage, a second input terminal for outputting the regulated bias voltage, and an output terminal; and
a third transistor coupling between the output terminal of the operational amplifier and the second input terminal of the operational amplifier.
7. The apparatus of claim 6 , wherein the third transistor includes a PMOS transistor having a first terminal connected to the power supply voltage terminal, a second terminal connected to the second input terminal of the operational amplifier, and a third terminal connected to the output terminal of the operational amplifier.
8. An apparatus comprising:
a bias generator configured to generate a temperature complementary voltage, the bias generator including:
a current source having a first terminal coupled to a power supply voltage terminal and a second terminal driving a bias voltage; and
a first transistor and a second transistor coupled in series between the second terminal of the current source and a ground terminal;
a regulator configured to regulate the bias voltage by using the temperature complementary voltage and outputting a regulated bias voltage; and
a ring oscillator configured to receive the regulated bias voltage and generating an oscillation signal based on the regulated bias voltage.
9. The apparatus of claim 8 , wherein the first transistor includes a NMOS transistor having a first terminal, a second terminal and a third terminal connected to the first terminal; and
the second transistor includes a PMOS transistor having a first terminal connected to the second terminal of the NMOS transistor, a second terminal and a third terminal connected to the ground terminal.
10. The apparatus of claim 9 , wherein the temperature complementary bias voltage VR 1 is substantially equal to as follows:
VR 1≈ VTp+VTn
where VTp and VTn are the threshold voltages for the PMOS transistor MP 1 and the NMOS transistor MN 1 , respectively.
11. The apparatus of claim 10 , wherein the ring oscillator includes a complementary metal oxide semiconductor (CMOS) ring oscillator having:
a cascade of inverters with odd number of stages in a ring shape, the regulated bias voltage and outputting an inverted bias voltage; and
a frequency counter the inverted bias voltage, and counting the inverted bias voltage according to a reference clock to generate the oscillation signal.
12. The apparatus of claim 11 , wherein the regulator includes:
an operational amplifier including a first input terminal for receiving the bias voltage, a second input terminal for outputting the regulated bias voltage, and an output terminal; and
a third transistor coupling between the output terminal of the operational amplifier and the second input terminal of the operational amplifier.
13. The apparatus of claim 12 , wherein the third transistor includes a PMOS transistor having a first terminal connected to the power supply voltage terminal, a second terminal connected to the second input terminal of the operational amplifier, and a third terminal connected to the output terminal of the operational amplifier.
14. An apparatus comprising:
a bias generator configured to generate a complementary-to-absolute-temperature (CTAT) bias voltage, the bias generator includes a current source driving a bias voltage, and a first transistor coupled with a second transistor in series between the bias voltage and a ground terminal;
a regulator configured to regulate the bias voltage by using the CTAT bias voltage and outputting a regulated bias voltage; and
a ring oscillator configured to receive the regulated bias voltage and generating an oscillation signal based on the regulated bias voltage, wherein the ring oscillator includes a complementary metal oxide semiconductor (CMOS) ring oscillator having:
a cascade of inverters with odd number of stages in a ring shape, configured to receive the regulated bias voltage and outputting an inverted bias voltage; and
a frequency counter configured to receive the inverted bias voltage, and counting the inverted bias voltage according to a reference clock to generate the oscillation signal.
15. The apparatus of claim 14 , wherein the
current source includes a first terminal coupled to a power supply voltage terminal and a second terminal driving the bias voltage.
16. The apparatus of claim 14 , wherein the first transistor includes a NMOS transistor having a first terminal, a second terminal and a third terminal connected to the first terminal; and
the second transistor includes a PMOS transistor having a first terminal connected to the second terminal of the NMOS transistor, a second terminal and a third terminal connected to the ground terminal.
17. The apparatus of claim 16 , wherein the CTAT bias voltage VR 1 is substantially equal to as follows:
VR 1≈ VTp+VTn
where VTp and VTn are the threshold voltages for the PMOS transistor MP 1 and the NMOS transistor MN 1 , respectively.