IP Library Granted Patent US 9,627,816
Granted Patent B2
US 9,627,816 · App. 15/146,019 · Granted Apr 18, 2017

High speed grounded communication jack

Inventors: Brett D. Robinson (Chino, CA); Justin Wagner (York, PA)
Assignee: SENTINEL CONNECTOR SYSTEM INC.
H01R13/6581H01R13/6474H01R24/64H01R13/6658H01R2107/00Y10T29/49165
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Quick Facts
Patent No.
US 9,627,816
App. No.
15/146,019
Granted
Apr 18, 2017
Kind
B2
Abstract

A method of manufacturing a high speed jack, the method including the steps of forming a housing including a port for accepting a plug, the port including a plurality of pins each connected to a corresponding signal line in the plug, forming a shielding case surrounding the housing, forming a top layer of a substrate, a first shielding layer on a first side of the top layer in the substrate, a second shielding layer adjacent the first shielding layer in the substrate, and forming a bottom layer adjacent to the second shielding layer, forming a plurality of first vias extending through the substrate with each first via being configured to accommodate a pin on the housing, forming a plurality of second vias extending through the substrate with each second via being configured to accommodate a pin on the housing.

Claims (40)

1. A high speed communication jack including:

a housing including a port for accepting a plug, the port including a plurality of pins each connected to a corresponding signal line in the plug;

a shielding case surrounding the housing;

a circuit board in the housing having

a substrate,

a plurality of first vias extending through the substrate with each first via being configured to accommodate a pin on the housing,

a plurality of second vias extending through the substrate with each second via being configured to accommodate a pin on the housing,

a first set of traces on a top layer of the substrate that connects at least one first via with at least one corresponding second via;

a first shielding layer on a first side of the top layer in the substrate;

a second shielding layer adjacent the first shielding layer in the substrate; and

a second set of traces on a side of the substrate opposite the top layer that connects at least one first via with at least one second via.

2. The jack of claim 1 wherein the second set of traces connect different vias that the vias connected on the top surface.

3. The jack of claim 1 including a first isolation region on the top surface between the first set of traces.

4. The jack of claim 1 including a second isolation region on the top surface between a second set of traces.

5. The jack of claim 1 wherein the first shielding layer is covered in a conductive material.

6. The jack of claim 5 wherein the conductive material does not cover an area around the periphery of the first vias and second vias.

7. The jack of claim 5 wherein the conductive material is comprised of copper and finished silver.

8. The jack of claim 1 wherein the second shielding layer is covered in a conductive material.

9. The jack of claim 8 wherein the conductive material does not cover an area around the periphery of the first vias and second vias.

10. The jack of claim 8 wherein the conductive material is comprised of copper and finished silver.

11. A method of manufacturing a high speed jack, the method including the steps of

forming a housing including a port for accepting a plug, the port including a plurality of pins each connected to a corresponding signal line in the plug;

forming a shielding case surrounding the housing;

forming a top layer of a substrate,

a first shielding layer on a first side of the top layer in the substrate;

a second shielding layer adjacent the first shielding layer in the substrate; and

forming a bottom layer adjacent to the second shielding layer,

forming a plurality of first vias extending through the substrate with each first via being configured to accommodate a pin on the housing,

forming a plurality of second vias extending through the substrate with each second via being configured to accommodate a pin on the housing,

forming a first set of traces on a top layer of the substrate that connects at least one first via with at least one corresponding second via;

forming a second set of traces on a side of the substrate opposite the top layer that connects at least one first via with at least one second via.

12. The method of claim 11 , wherein the second set of traces connect different vias that the vias connected on the top surface.

13. The method of claim 11 including the step of forming a first isolation region on the top surface between the first set of traces.

14. The method of claim 11 including the step of forming a second isolation region on the top surface between a second set of traces.

15. The method of claim 11 wherein the first shielding layer is covered in a conductive material.

16. The method of claim 15 wherein the conductive material does not cover an area around the periphery of the first vias and second vias.

17. The method of claim 15 wherein the conductive material is comprised of copper and finished silver.

18. The method of claim 11 wherein the second shielding layer is covered in a conductive material.

19. The method of claim 18 wherein the conductive material does not cover an area around the periphery of the first vias and second vias.

20. The method of claim 18 wherein the conductive material is comprised of copper and finished silver.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2017
From: ROBINSON, BRETT
To: SENTINEL CONNECTOR SYSTEM INC.
Reel/Frame 041161/0013 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2016
From: WAGNER, JUSTIN
To: SENTINEL CONNECTOR SYSTEM INC.
Reel/Frame 038922/0135 →
Continuity (4)
Continuation In Part 14504088 · Oct 1, 2014
Continuation In Part 13739214 · Jan 11, 2013
Provisional Application 61598288 · Feb 13, 2012
Related Publication 20160248205A1 · Aug 25, 2016