Method of manufacturing a device having a shield plate dopant region
Forming a transistor transistor includes forming a surface region, a gate, a source dopant region, a drain dopant region, a drift dopant region, a set of electrically conductive shield plates, and a shield plate dopant region. A sidewall of the gate aligns with a drain side boundary of the surface region. The drain dopant region is formed within the surface region on the drain side. The drift dopant region is formed within the surface region between the drain side boundary and the drain dopant region. The set of electrically conductive shield plates includes a first shield plate overlying the drift dopant region. The shield plate dopant region is formed within the drift dopant region and underlies the set of shield plates.
1. A method of manufacturing a transistor, the method comprising:
forming a gate on a surface region of a semiconductor substrate, the gate having a sidewall that aligns with a gate region boundary, wherein the gate region boundary defines a lateral boundary for a channel region within the surface region under the gate;
forming a drift dopant region within the surface region on a first side of the gate, wherein the drift dopant region extends from the gate region boundary;
forming a set of electrically conductive shield plates that overlies the sidewall of the gate and a portion of the drift dopant region;
forming a shield plate dopant region within the drift dopant region and underlying at least one shield plate of the set of shield plates; and
forming a drain dopant region within the surface region on the first side of the gate, wherein the drift dopant region is disposed between the channel region and the drain dopant region.
2. The method of claim 1 , wherein forming the set of electrically conductive shield plates comprises forming a plurality of electrically conductive shield plates having at least a first and a second shield plate, wherein the first shield plate is a topmost shield plate having an end that extends closer to the drain dopant region than an end of the second shield plate, wherein the shield plate dopant region does not extend beyond the end of the first shield plate.
3. The method of claim 1 , wherein forming the set of electrically conductive shield plates comprises:
forming a first and topmost shield plate overlying a first portion of the drift dopant region;
forming a second shield plate underlying the first shield plate and overlying a second portion of the drift dopant region.
4. The method of claim 3 , wherein the first shield plate is formed to have an end located further from the gate region boundary than an end of the second shield plate, and wherein an entirety of the shield plate dopant region is formed between the gate region boundary and a boundary that aligns with the end of the first shield plate.
5. The method of claim 4 , wherein the shield plate dopant region is formed to only partially underlie the second shield plate.
6. The method of claim 1 , wherein the shield plate dopant region is formed to only partially underlie the at least one shield plate of the set of shield plates.
7. The method of claim 1 , wherein the shield plate dopant region is formed to fully underlie the at least one shield plate of the set of shield plates.
8. The method of claim 1 , wherein the shield plate dopant region is formed a gap distance away from the gate region boundary.
9. The method of claim 8 , wherein the shield plate dopant region is formed in a location such that the gap distance less than half a length of the drift dopant region.
10. The method of claim 1 , wherein the shield plate dopant region is formed having a width within a range of 0.2 microns to 1.1 microns.
11. The method of claim 1 , wherein the shield plate dopant region is formed using at least one of arsenic, phosphorous, or antimony dopant ions.
12. The method of claim 1 , wherein the shield plate dopant region is formed using dopant ions having an opposite conductivity type as a conductivity type of the channel region.
13. The method of claim 1 , wherein the shield plate dopant region is formed using dopant ions having a same conductivity type as a conductivity type of the drift dopant region.
14. The method of claim 1 , wherein the transistor is manufactured as a laterally diffused metal-oxide semiconductor field-effect transistor.
15. The method of claim 1 , wherein the shield plate dopant region is formed partially within the channel region.
16. The method of claim 1 , wherein forming the set of electrically conductive shield plates comprises forming a plurality of shield plates, wherein the shield plate dopant region is formed to underlie only a subset of the plurality of shield plates.
17. The method of claim 1 , wherein the drift dopant region is formed to have a depth within a range of 0.6 micron to 4 microns.
18. A method of manufacturing a semiconductor device, the method comprising:
forming a gate dielectric overlying a surface region of semiconductor material;
forming a gate electrode overlying the gate dielectric, the gate electrode having a first sidewall that aligns with a first gate region boundary and a second sidewall that aligns with a second gate region boundary;
forming a drift dopant region disposed within the surface region and extending from the second gate region boundary to an area beyond the second gate region boundary;
forming a set of electrically conductive shield plates overlying a portion of the drift dopant region; and
forming a shield plate dopant region disposed within the drift dopant region and underlying the set of shield plates.
19. The method of claim 18 , wherein forming the set of shield plates comprises forming a plurality of shield plates having a topmost shield plate, wherein an entirety of the shield plate dopant region is located between the second gate region boundary and a boundary aligned with an end of the topmost shield plate.
20. The method of claim 18 , wherein the shield plate dopant region is formed using dopant ions having a same conductivity type as dopant ions within the drift dopant region.